JPH0473684A - Display control device and display control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a display control device, and more specifically, the present invention relates to a display control device, and more specifically, a display that is updated by applying an electric field or the like using, for example, a ferroelectric liquid crystal as an operating medium for updating the display. The present invention relates to a display control device for a display device including a display element that can maintain a state.

[Prior Art] Display devices are generally used in information processing systems as information display means that performs the function of visually expressing information, and the CR7 display device is widely known as such a display device. .

In display control in a CR7 display device, the writing operation of the CRH on the system side to the video memory as a display data buffer on the CRT side and the operation of reading display data from the video memory and displaying one display by a CRT controller on the CRT side are independent of each other. is executed.

In the case of CRT display control as described above, the writing of display data to a video memory for changing display information and the operation of reading and displaying display data from the video memory are independent, so the information processing The program on the system side does not need to consider display timing or the like at all, and has the advantage that desired display data can be written at any timing.

However, on the other hand, since CRTs require a certain length in the thickness direction of the display screen, their overall volume is large (which makes it difficult to miniaturize the entire display device. The degree of freedom in using an information processing system using the display as a display device, that is, the degree of freedom in terms of installation location, portability, etc., is impaired.

A liquid crystal display (hereinafter referred to as LCD) can be used to compensate for this point. That is, according to the LCD, the entire display device can be made smaller (particularly thinner). In such an LCD0, the above-mentioned ferroelectric liquid crystal (hereinafter referred to as FLC) is used.
A display device using a liquid crystal cell (hereinafter referred to as FLCD: FLC display)
One of its features is that its liquid crystal cell maintains its display state against the application of an electric field. That is, in FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in a first stable state or a second stable state depending on the direction of electric field application, and when the electric field is removed, maintain their respective orientation states. Due to such bistability of FLC molecules, FLCD has memory properties.

Details of such FLCi3 and FLCD are described in, for example, Japanese Patent Application No. 1983-76357.

As a result, when driving an FLCD, unlike a CRT or other liquid crystal display, there is a time margin in the cycle of continuous refresh drive of the display screen, and there is also a time margin in the cycle of continuous refresh drive of the display screen. , it becomes possible to perform partial rewriting drive that updates the display state of only the changed portion on the display screen.

[Problems to be Solved by the Invention] Therefore, if appropriate and timely partial rewrite driving can be performed in FLCD, the advantages of FL(:D) will be further increased.

In addition, this more flexible F is used as a display device for information processing systems.
The ability to use LCDs interchangeably with CRTs increases the flexibility and value of the system.

From the above viewpoint, it is possible to consider a display control mode in which predetermined partial rewriting is given priority over other partial rewriting of display information. An example of such a display is a display of cursor movement, and the display state of this display must be changed in real time (intuitively) in accordance with the operation of a mouse or the like by the operator.

If such a display is defined as an event, a configuration for performing partial rewriting for the event according to the priority order among multiple events is proposed, for example, in Japanese Patent Application Laid-Open No. 2-934 by the applicant.
It is disclosed in No. 91. However, in display control with this configuration, when a partial rewrite related to an event is performed, the information processing system side provides information for identifying this process to the display device side. Therefore, a control program for an information processing system using such a display device is significantly different from a control program for an information processing system using the above-mentioned CRT as a display device.

As a result, it becomes difficult to configure an information processing system that is compatible with FLCD and CRT.

On the other hand, when an FLCD is used as a display device of an information processing system while being compatible with a CRT, an essential problem arises in its configuration. That is, the CPU on the system side only transfers display data related to display updating and its address to the display device side. Therefore, there arises the problem of how to distinguish the partial rewriting related to the above-mentioned event from other partial rewriting, and as a result of this discrimination, how to prioritize the partial rewriting related to the event.

The present invention has been made in view of the above-mentioned problems, and it is possible to easily and reliably capture a specific event and display it in priority to other partial rewriting displays, and it also provides an information processing system. An object of the present invention is to provide an FLCD display control device that is compatible with a CRT without significantly changing the side software.

By the way, recently, with the aim of reducing the burden on the CPU installed in the system, data related to a predetermined event is not displayed by accessing the video memory of the CPU, but rather by displaying such data generation circuit and video memory. Systems have appeared that are equipped with a compositing circuit that performs compositing with the content, and in which the CPU simply gives instructions on the display position of such data. This is what is called a hard cursor, and takes advantage of the fact that the data of the cursor itself is fixed. That is, if the cursor movement display is regarded as an event, it is sufficient for the CPU to simply change the display position information in response to such an event.

However, since the FLCD used as a display device has a memory property, it is desired to take measures that are suitable for and utilize the characteristics of the FLCD. That is, it is desirable to appropriately control FL(:D) when displaying or moving a hard cursor, and it is also desirable to be able to respond not only to the hard cursor but also to other events by utilizing the characteristics of the FLCD.

Therefore, a further object of the present invention is to enable event-related data to be appropriately synthesized with FLCD.

[Operation] According to the above configuration, when a display state is partially changed in response to an event, a requested address is displayed according to the changed part of the display data recorded by, for example, a video memory as a storage means. Image data related to the event is combined with the data.

[Means for Solving the Problems] To this end, the present invention provides a display control device for a display device in which the display state of pixels can be partially changed, comprising: a storage device for storing data to be displayed on the display device; In displaying the data on the display device, the method further comprises a composition means for synthesizing data to be synthesized according to the graphic event for the data to be displayed at a position specified according to the graphic event. It is characterized by

(Margin below) [Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

(System Configuration) FIG. 1 is a block configuration diagram of the entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, 11 is a C that controls the entire information processing system.
PU, 12 is a system bus consisting of an address bus, a control bus, and a data bus; 13 is a main memory used for storing programs and as a work area;
4 is a DMA controller (DirectM) that transfers data between the memory and the I10 device without going through the CPU II.
memory Access Controller (hereinafter referred to as DMAC), 15 is an Ethernet (XEROX
LAN (Local Area Network) 16, 17 is a ROM
, SRAM, R5232C specification interface, etc., for connecting I10 devices, 18 is a hard disk device, 19 is a floppy disk device, 20 is a disk' interface for the hard disk device 18 and floppy disk device 19, and 21 is, for example, a laser. A high-resolution printer such as a beam printer or an inkjet printer; 22 is a printer interface for the printer 21; 23 is a keyboard 124 for inputting characters such as letters and numbers; 25 is a mouse, which is a pointing device; The interface 26 for the mouse 24 is an FLCD (FLC display) that can be constructed using a display device disclosed in Japanese Patent Laid-Open No. 63-243993 by the present applicant, for example.
, 27 is an FLCD interface for the FLCD 26.

(Display control device) Figure 2 shows an FLC as an embodiment of the display control device of the present invention.
2 is a block diagram showing an example of the configuration of a D interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 44 are data bus drivers. Address data from CPUII is
From the address bus driver 31 to the memory controller 4
0 and one input portion of the address selector 35, and is selectively applied to and stored in the FIFO type memory 36 or 37 by switching the first switch S1. That is, these memories 36 and 3
7 (hereinafter referred to as FIFO (A) and FIFO (B), respectively)
J) reads data in the order it was written.
This is an IFO (First In First Out) memory, and the address data written in these memories 36 and 37 is selectively read out by switching the second switch S2.

The address data read from these memories 36 or 37 is the same as the address data from the address counter 38 (described later) (partial rewrite request circuit 100 described later).
The address data from the address selector 35 is selectively applied to the other input section of the address selector 35 by switching the selector 50. The address counter 38 generates address data for refreshing the entire screen line-sequentially, and the timing of generation of the address data is controlled by the synchronization control circuit 39. This synchronous control circuit 39 includes the switches Sl, S2 and the selector 5.
0 switching control signal S 1 (A/B), S2
(A/B), a select control signal 5LCT, and a data transfer request signal to a memory controller 40 to be described later.

Furthermore, the partial rewrite request circuit 100 and the synchronization control circuit 39 exchange a request signal REQ requesting partial rewriting and an acknowledge signal ACK when an event occurs (in this example, when the cursor is moved).

Control signals from the CPU II are applied from the control bus driver 32 to the memory controller 40, which generates control signals for the sampling counter 34, address selector 35, and video memory 41, which will be described later. The sampling counter 34 performs a counting operation based on the step signal from the memory controller 40, and the synchronous control circuit 39
A control signal C is generated. In addition, the address selector 35
, selects one of the two address data given to the input section of the address selector 35 and supplies it to the video memory 41 based on a control signal from the memory controller 40 .

The video memory 41 stores display data.
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads display data via the data bus driver 33.

The display data written in the video memory 41 is supplied to the image data synthesis circuit 200 via the driver receiver 42, where appropriate image synthesis is performed and then the display data is transferred to the FLCD.
26 and displayed.

Further, the driver receiver 42 provides a synchronization signal from the FLCD 26 to the synchronization control circuit 39. FLCD26
A temperature sensor 26a that detects the temperature of the FLC is incorporated in the .

Further, setting data, which will be described later, from the CPU II is provided to the synchronization control circuit 39 via the data bus driver 43. Further, the output signal of the temperature sensor 26a is transferred to the CPU II via the data bus driver 44.

Note that 47 is engaged with the data bus on the system bus 12 and requests the partial rewrite request circuit 100 to send the video memory 41
48 is a bus driver for setting the position information of image data such as a cursor (hereinafter referred to as compositing data) to be synthesized with internal data; It is a receiver for

The FLCD interface main body within the broken line indicated by the reference numeral 300 and the circuit section indicated by the reference numeral 400 including the partial rewrite request circuit 10013 and the image data synthesis circuit 200 may be configured as one unit, but they may be configured separately. circuit section 40
0 can be attached to the FLCD interface main body 300. That is, the circuit section 400 may be an external circuit for the FLCD interface main body 300,
In this case, the FLCD interface main body 300 is preferably installed when it is applied to, for example, a system compatible with the so-called hard cursor function described above. In other words, when displaying or moving synthesis data such as a cursor in a system that supports a hard cursor function, the CPU 1.
Even in a system in which the video memory 41 is not accessed by the video memory 41, such an event is detected, partial rewriting is started accurately and quickly, and image composition can be realized.

FIG. 3 shows a configuration example of a partial rewrite request circuit 100 compatible with a hard cursor according to this example.

Here, 101 and 102 are position registers (referred to as position registers and ■, respectively) for storing the old position or new position of the cursor, and they alternately latch values in response to settings from CPLIII. That is, when displaying or moving the cursor, one memorizes the old position and the other memorizes the new position. A cursor size register 105 is used to store the size of the cursor to be displayed, and the size is set by the CPU 1.

When displaying or moving the cursor, the CPU II sets the new position of the cursor in position register I or ■ and sets its size in the cursor size register 105, but does not set the size unless the size has changed (but good.

107 is a request control circuit, which controls the position register or H
When the new position of the cursor is set to , the contents of the position register ■ or I that stores the old position are loaded into the request address counter 109, and the synchronization control circuit 39
A partial rewrite request signal REQ is sent to update the cursor. Then, when an acknowledge signal ACK is supplied from the synchronization control circuit 39, the request address counter 109
The requested address counter 109 sequentially counts up the line address at the old position by the cursor size (number of lines) set in the cursor size register 105 and sends the value to the selector 50 side. Since the FLC has a memory property, the cursor at the old position is immediately erased prior to updating the cursor, as will be described later. Specifically, only the data in the video memory 41 at that position is erased. This is a group of line addresses used for redisplay.

Thereafter, the request control circuit 107 loads the value of the position register storing the new position into the counter 109 and sends the signal REQ, and in response to the input of the signal ACK, the request control circuit 107 performs the same process as above regarding the new position. make the action take place. The line address group output at this time is used to display the cursor at the movement destination.

The cursor is moved (updated) by repeating the above operations every time a new cursor position is set from the CPU II. Note that in order to alternately set new positions in the position registers I or (2) and alternately load the counter 109, for example, a toggle-operated switch may be inserted at an appropriate location.

FIG. 4 shows a configuration example of an image data synthesis circuit 200 compatible with a hard cursor according to this example.

Here, 201 is a position register in which the new position of the cursor updated by CPIJII is set, and 205 is a cursor size register in which the cursor size is also set.

FIG. 5 is an explanatory diagram of data stored in these registers. As shown in FIG. 0, the upper left corner of the display screen is the origin (0
, 0), and the relative path M (X, Y) from that point becomes the cursor position and is stored in the position register 201. On the other hand, its width W and height H are the cursor size register 2.
It is set to 05.

Note that the contents stored in the position registers 101 and 102 and the cursor size register 105 in the partial rewrite request circuit 100 shown in FIG. 3 may be the same as the position register 201 and the cursor size register 205, respectively.
Since the partial rewrite request circuit 100 in FIG. 3 only needs to output a line address, only data in the sub-scanning direction V (Y and H, respectively) is set in the position registers 101, 102 and the cursor size register 105. Alternatively, the contents of the cursor size register 205 in FIG. 4 may be changed only when the cursor size is changed, as described above.

In FIG. 4, 10 and AD are FLCD, respectively.
These are the identification signal and address/data signal transmitted from the video memory 41 of the interface main body 300. To explain these signals using FIG. 6, the FLCD interface main body 300 outputs a data group of one main scanning line (H direction line in FIG. 5) in response to the horizontal synchronization signal H3YNC from the FLCD 26. This data group is a data group from the leftmost pixel to the rightmost pixel on the right side of one main scanning line ("Data 1", "Data 2", etc.).
), the line address of the line in question is added to the beginning of this data group and sent out as an address/data signal AD. On the other hand, in order to identify that the beginning of the signal AD is an address, "
1'' When "data 1", "data 2", . . . are output, an identification signal ID that becomes "0" is sent out.

Referring again to FIG. 4, 207 is a sub-scanning comparison circuit. The sub-scanning comparison circuit 207 includes registers 201 and 205.
Based on the value of , it is determined whether the image data sent from the FLCD interface body 300 is included in the line on which the cursor should be displayed, based on the line address at the beginning of the image data group. That is, it is determined whether the line address to be displayed is currently between Y-Y+H (see FIG. 5). If it is determined that there is a match between the two, a match signal is sent to the main scanning counter 209.
Send to.

The main scanning counter 209 counts the number of pixels in the main scanning direction based on this coincidence signal, and calculates the X value set in the position register 201 and the cursor size register 205.
Based on the W value set in , it is determined whether the current pixel is in the range of X to x10W. If it is within that range, the cursor display data is expanded, a corresponding position in the cursor RAM is specified, data at that position is read out, and a synthesis instruction is given to the logic synthesis circuit 213.

In the logic synthesis circuit 213, when the synthesis instruction signal is not given from the main scanning counter 209, the address data signal A/D from the FLCD interface main body 300 is output as is to the FLCD 26, and when there is a synthesis instruction, the cursor RAM 211 is output to this. It performs logical operations on the data read from and outputs the synthesized data.

The following operations are performed by the configurations shown in FIGS. 3 and 4.

That is, the current position (x, y) of the cursor is stored in one of the position registers 101 and 102 in the partial rewrite request circuit 100 and in the position register 2 in the image data synthesis circuit 200.
01, and the cursor is displayed based on the data held in the registers 201-205. Therefore, even if the line on which the cursor is displayed is accessed during a refresh cycle or partial rewrite cycle, which will be described later,
The cursor is displayed at that position on that line, and the cursor is not erased by the access.

On the other hand, when moving the cursor, ((X, Y) → (
X', Y')), the data at the new position is stored in registers 101, 1
02 (1) Set to the other and register 201
is set to First, from the old position “Y” to “H”
"The line address for the line is output, and in response, the corresponding line address and data in the video memory 41 are output to the image data synthesis circuit 200. At this time,
Since the contents of the register 201 in the circuit 200 have already been updated, the data is directly transferred to the FL without being synthesized.
Displayed on CD26. Therefore, the cursor display is erased from the line where the cursor was displayed up until then. After this, “ from the new position “Y”
In response to the output of the line address for the H'' line, cursor data is synthesized with the data of the line according to the contents of registers 201 and 205, and the new position (X',
A cursor is displayed at Y').

(Operation example) In the above configuration, when the CPU II changes the display data in the video memory 41, the address signal of the video memory 41 corresponding to the desired data rewriting is sent to the memory controller 40 via the address bus driver 31. Here, arbitration is performed between the CPU II memory access request signal and the data transfer request signal from the synchronization control circuit 39. When the CPU accessing side obtains the right, the memory controller 40 switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 41.

At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, the CPU access address 20 is transferred to the FIFO (
A) 36 or FIFO (B) 37, and used when transferring display data, which will be described later. In this way C
The display data access method seen from PUII is the conventional C
This is no different from the case of a system using RT as an indicator.

It also reads data from the video memory 41 and displays it on the FLCD.
26, a data transfer request is generated from the synchronization control circuit 39 to the memory controller 40, and the address counter 38 or FIFO side address address selector 3 is sent as the address to the video memory 41.
5 and the memory controller 4
By generating a control signal for data transfer from 0, data at the corresponding address is transferred from the memory cell to the shift register, and is output to the driver 42 by the control signal of the serial port.

The synchronization control circuit 39 refreshes the entire screen line by line in units of multiple lines based on the horizontal synchronization signal H3YNC from the FLCD 26,
Timing is generated to alternately generate partial rewrite cycles in which lines accessed by UII are rewritten. Here, the full refresh cycle is to perform rewriting λ sequentially downward from the top line (first line) on the display screen, and when it reaches the bottom line, return to the top line again and rewrite. It is something that is repeated. Furthermore, an access line rewriting cycle is a cycle in which a line accessed from the CPU II is rewritten within a predetermined time period immediately before the cycle.

In this way, basically, in this example, the entire screen of the FLC display 26 is sequentially refreshed (line) and the line accessed by the CPU II is rewritten in order to change the display contents. The division is performed alternately, but when an instruction to move the cursor is given, the latter operation period is used to quickly update the cursor display.

First, with reference to FIG. 7, the basic operation of this example will be described in which a refresh operation and a line rewriting operation are performed alternately in a time-sharing manner without performing a cursor movement display. Here, an example will be shown in which the refresh cycle is performed in units of 4 lines, and the access line rewrite cycle is performed in units of 3 lines.

In FIG. 7, REE/AC3 is a timing that causes a full refresh cycle and an access line rewriting cycle to occur alternately. Indicates a rewrite cycle. Further, ``■'' represents the full refresh cycle time, and Tb represents the access line rewrite cycle time. In this example,
Ta:Tb"4:3, but an optimal value can be selected depending on the required refresh rate, etc.

That is, by increasing the ratio of T, the refresh rate can be increased, and by increasing the ratio of TI, the responsiveness of partial changes can be improved.This aspect will be described later.

To explain the states of FIFO (A) 36 and FIFO (B) 37, when switch Sl is connected to FIFO (A) 36 side (state A/B = 1), CPUI
The address of the line accessed by I is FIFO (A)
36 samples and stored. On the other hand switch S
1 is connected to the FIFO (B) 37 side (A/B=
O) The line address accessed by the CPU II is stored in the FIFO (B) 37. In addition, switch S2
is connected to the FIFO (A) 36 side (A/B=1
), the address stored in the FIFO (A) 36 is output, and when switch S2 is connected to the FIFO (B) 37 side (A/B = 0), the address stored in the PIFO (B) 37 is output. be done.

One refresh of the entire screen is completed, and FLCDz6
outputs the vertical synchronization signal VSYNC, or when a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle returns to the O-th line, and the FLCD 26
Each time the horizontal synchronization signal H3YNC is applied via the synchronization control circuit 39, the count is sequentially increased to "1", "2°", "3°". During this time, line Ll is sent from CPU II.
, L2. When the address of L3 is accessed, since switch S1 is connected to FIFO (A) 3B, Ll, L2 . The address of L3 is stored here, and then when switch S2 is connected to FIFO (A) 36, Ll, L2 . The L3 address is output from here,
Ll, L2 . as output lines. L3 is selected. Here, the switching signal of the selector 50 is given by the signal 5LCT from the synchronization control circuit 39, and in the line access cycle, FIFO (A), FI are given as output line addresses.
Switched to FO (B) side.

At this time, since the switch S1 is connected to the FIFO (B) 37 side, the access address is stored on the FIFO (B) 37 side. In the refresh cycle, the selector 50 is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In Fig. 7, lines “4”, “5”, “6”, and “7”, which are the continuation of the previous cycle, are output after the line output of L3.The above operation is repeated in the same manner, but the FIFO The reason for preparing two is to sample the memory accessed address on one side and simultaneously output the sampled address on the other side without any contradiction and efficiently. In other words, the sampling period of the address is From the start of output of the access line of the other FIFO until the end of the full refresh cycle,
After the completion of the full refresh cycle, at the same time a rewriting cycle of the access line that outputs the address sampled in the previous sampling period begins, the other FIF
The address sampling period of O will begin.

As described above, in the basic operation of this example, refresh cycles and line rewrite cycles are alternately repeated, and the seventh
In the figure, the repetition period is T, with 7 lines as one unit:
Although the explanation was given with T = 4:3, in this example, the environmental conditions such as temperature, the type of data to be displayed, or even F
The ratio between T and T can be changed depending on the refresh rate required depending on the difference in the display device material of the LCD. In other words, the ratio of ■ (corresponds to the number of lines M in one refresh cycle; that is, Ta=Mx(
By increasing the period of HSYNC), the refresh rate can be improved, and a good display state can be obtained, for example, even when the responsiveness of the low-temperature special FLC element is low or when displaying an image. On the other hand, if the ratio of Tb (corresponding to the number of lines N in one partial rewrite cycle, that is, 7b: N This means that it can be used in cases where a high refresh rate is not required, such as at high temperatures or when displaying characters such as text.

Furthermore, in this embodiment, by making it possible to set the number of lines in the repetition cycle, the refresh cycle and partial rewriting ratio can be changed more precisely, allowing for more detailed optimization. For example, If the refresh rate must or should be given priority, if the number of lines in the repetition period is set to 40 lines and T: Tb = 4:1, then full refresh is performed for 32 lines and the access lines are rewritten. In addition, if you can or want to give priority to partial rewriting, if you set the number of lines in the repetition period to 10 lines and set T, :Tl, = 3:2, you can perform full refresh for 6 lines. Go and rewrite the access line 4
line can be done.

Furthermore, in this embodiment, within the range of the number of lines for partial rewriting set in this way, the actual number of lines for partial rewriting performed between refresh cycles is determined according to the number of lines accessed to cputt and the line access state. Try adjusting P. That is, the CPUI
By dynamically adjusting the Tb time according to the number of lines accessed by I, for example, unnecessary line rewriting cycles when accessed from CPU II is not often avoided,
Improve refresh rate. This makes it possible to dynamically optimize the relationship between motion followability and refresh rate.

This applies, for example, to the patent application No. 2-10 filed by the applicant.
This can be done according to the rules and structure disclosed in No. 5626.

Next, the operating state when there is an instruction to move and display the cursor will be explained using FIG. However, in this figure, for the sake of simplicity, the height of the cursor is set to H, which is "1".

In the device according to this example, the partial rewriting for displaying cursor movement is performed during the line access period, that is, the synchronization control circuit 39 in FIG. 2 responds to the request signal REQ only during the line access period. (J is output, and if there is an instruction to move the cursor during the refresh period, in the immediately following line access period,
If an instruction is given during the line access period, partial rewriting for the movement display is performed within that period. Note that even if an instruction is given during a line access period, if that period has expired and processing cannot be performed, the processing will be performed during the next line access period.

Now, FIG. 8 shows the process in which the cursor located on the line having the address EXI is moved to the position on the line having the desired address EX2, and then further to the position on the line having the address EX3. There is.

When moving from EXI to EX2, first, in order to erase the cursor on the line having the current address EXI, an access to that line is requested and the request circuit 100 sends the signal R.
EQ is sent to the synchronization control circuit 39. Synchronous control circuit 3
9 waits for the end of the refresh period, returns the signal ACK, switches selector 5°, and selects the address EXI.
be accepted. Accordingly, the address E
The line with XI is accessed and
As mentioned with respect to the figure, only the data in video memory 41 on that line will be displayed, ie the cursor will be removed from that line. EX2 Gara E
The manner of erasing when moving to X3 is also similar.

Next, in order to display the cursor on the line having the new address EX2, the request circuit 100 requests access to that line and sends out the signal REQ. In the case of this figure, the synchronization control circuit 39 immediately returns the signal ACK and , switches the selector 50 to accept that line address. As a result, the line having the address EX2 is accessed, and as described above, cursor data is synthesized at the folding position and a cursor is displayed. EX2 to E
The manner of erasing when moving to X3 is also similar.

In this figure, partial rewriting (11
However, depending on the processing speed of the synchronous control circuit 391 and the partial rewrite request circuit 100, the display on the EX2 and the output may be delayed.

In addition, in this example, to simplify the explanation, the line access period is assumed to be three lines, and the cursor height is set to "1," but in reality, as shown in Figure 5, the cursor has a height that spans multiple lines. Therefore, the line access period can be determined taking this into account.

(Other Embodiments) It goes without saying that the present invention is not limited to the above-described embodiments, and can employ various configurations and control methods.

For example, on the upper side, refresh periods and line access periods are alternately performed, cursor movement display is performed only during the line access period, and cursor movement display is performed with priority over normal line access. However, the cursor display is displayed even during the refresh period.
Alternatively, the display may be performed only during that period, and the priority of cursor display may be determined as appropriate. Further, instead of having a configuration in which the refresh period and the line access period are performed alternately, only one of them may be performed.

In addition, for example, a partial rewrite request circuit 1 compatible with a hard cursor may be used.
00 can also be configured as shown in FIG.

In FIG. 9, 121 is a difference register, and the first O
The old (current) position of the cursor (x,y) as shown in the figure
The absolute value ly+-yal of the difference between the value y1 in the sub-scanning direction V and the value of the folding position (xi, yz1 in the same direction) is set.

123 is a movement direction register, and when y+>yz, “
"1" is set when y+<yz.

125 is a cursor size register similar to the above;
The cursor height H and width W are set.

129 is a comparison control circuit that compares the contents of each register when executing the operation shown in FIG. 11 and outputs a load signal to the line address counter 133. 131 is a current line register in which the address of the line including the current position of the cursor is set. 1
33 is a line address counter, and the comparison control circuit 1
Current line register 13 according to the load signal of 29
1 is loaded, and from that value (line address), a group of line addresses that have been scanned are sequentially output and output to the selector 50. 137 is a request control circuit, which sends and receives signals REQ and ACH to and from the synchronization control circuit 39, and only for a period determined by the deviation between the old position (yl) and the fold position (y2) and the cursor size (H). , outputs an enable signal to the line address counter 133 to execute the above-mentioned increment and line address output.

FIG. 11 is a flowchart for explaining an example of the operation of the configuration shown in FIG.

There is a cursor movement instruction from CPLIII, and the difference register 121 and movement direction register 123 (and size register 125 if there is a change in cursor size)
If there is a setting to (step S1), the difference y+-ysl
It is determined whether the movement is less than 8, that is, less than the height of the cursor (step S3).

If the judgment is negative here, the current line register 13
The value of 1 (here, y+, which is the old position) is loaded into the line address counter 133 (step S5), and the signal RE
Send Q. Next, when the signal ACK is returned, the signal REQ is deactivated in step S9゜5ll), and the line address counter 133 is caused to perform a predetermined operation. next,
It is detected whether or not the address output for the line corresponding to the cursor height H has been completed, and if it has not been completed, step S
7 and repeats steps 87 to S13. In this process, as described above, the data in the video memory 41 for lines y to H is output to the image data synthesis circuit 200, and the new position of the cursor is held in the left image data synthesis circuit 200. Therefore, the cursor data is not combined, that is, the cursor is erased from its old position.

Next, in step S15, the new position (y2) determined by the old position (y,), the result of the difference (Iy, -y-l, and the movement direction) is set in the current line register 131,
In step S17, the same processing as in steps 35 to Sll is performed for H lines (step 519). This will cause the cursor to be displayed at the new position.

On the other hand, if the deviation between the old and new positions is less than H, the moving direction is first determined (step 521). Here, move the cursor to the bottom of the screen in the “+” direction, that is, 31+
If <yt, the same process as steps 37 to Sll above is performed (step 523).

Next, it is determined whether this process has been completed for H"13'+-ytl lines. This means that if Iy+-yxl<H, there is overlap between the new and old cursors, and H"13'+-ytl lines have been completed for both positions.
This is based on the fact that even if you do not access line by line (access for 2H lines), it is sufficient to access the number of lines equal to 2H lines minus the number of overlapping lines (2H-(H-ly+-). yzl):)I+Iy+-
ytl). This allows line access to be performed with high efficiency, and in the process, it is ensured that the cursor at the old position is erased and the cursor is displayed at the new position. Note that after completing that line, step S
15 is performed, and y2 is set in the current line register 131 (step 527).

If yt>31g in step S21, first set y2 in the current line register 131 by the same process as step S15 (step 531),
If the same processing as steps S5 to S], 1 and S27 (steps S33 and 535) is performed, the cursor at the old position can be erased and displayed at the new position efficiently (and reliably).

Incidentally, in the above explanation, the present invention has been explained with reference to an example corresponding to the hard cursor function, but examples of data to be synthesized with data in the video memory (composition data) include other data such as a video window or a message. There are superimpositions, overlays of some form, etc., and the present invention can effectively deal with these as well.

In these cases, for example, referring to the partial rewrite request circuit shown in FIG. 3, only when movement of the combining data occurs, loading of the combining data to the request address counter 109 at the old position and partial rewriting to the synchronization control circuit 39 is performed. A request signal REQ is sent. When an acknowledge signal ACK is supplied from the synchronization control circuit 39, counting permission is given to the request address counter 109, and the request address counter 109 has the same configuration as the cursor size register 105. (
While sequentially counting up the line address of the old position by the number of lines), the value is sent to the selector 50 side. Since the FLC has a memory property, the compositing data at the old location is immediately erased prior to updating the compositing data, specifically, the video memory 41 at that location, as described later. This is a group of line addresses that are used to redisplay only the data of .

Thereafter, the request control circuit 107 loads the value of the position register storing the new position into the counter 109 and sends the signal REQ, and in response to the input of the signal ACK, the request control circuit 107 performs the same process as above regarding the new position. An action (abbreviated as action A) is performed.

The line address group output at this time is used to display the synthesis data at the destination. In addition,
If there is no movement, this operation A may be repeated at a constant cycle faster than the refresh rate of the entire screen.

On the other hand, the image data synthesis circuit can also have the same configuration and system as described above; for example, it is sufficient to change the cursor RAM 211 in FIG. 4 to a frame buffer for displaying data for synthesis.

Further, a circuit section 300 including these circuits 100 and 200
may be configured for multiple types of synthesis data. Further, such a circuit section 300 may be provided for each purpose, or a plurality of circuit sections 300 may be appropriately installed to switch the performance as a display control circuit.

Furthermore, by taking advantage of the fact that the FLCD element has a memory property, a synthesis circuit may be configured to be able to handle a plurality of types of events, and also be able to switch between events.

(The following is a blank space) [Effects of the Invention] As is clear from the above description, according to the present invention, the address requested according to the changed part of the display data stored in the video memory as the storage means, for example, is The image data related to the event is synthesized.

With this, for example, a hard cursor for cursor display can be configured as appropriate for the FLCD,
Furthermore, partial rewriting specific to FLCD can be effectively utilized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the overall configuration of an information processing device incorporating a display control device of the present invention, FIG. 2 is a block diagram of a display control device according to an embodiment of the present invention, and FIG. 4 is a block diagram showing an example of the configuration of the image data synthesis circuit; FIG. 5 is an explanatory diagram for explaining a cursor as an example of data to be synthesized; FIG. 6 is an explanatory diagram of signals output by the FLCD main body according to this example, FIGS. 7 and 8 are timing charts for explaining two examples of the operation of this example device, and FIG. 9 is a partial rewrite request circuit. FIGS. 10 and 11 are block diagrams showing other configuration examples. FIGS. 10 and 11 are explanatory diagrams of its operation and a flowchart of an example of its operation. 11... CPU, 12... System bus, 13... Main memory, 14... DMA controller, 15... LAN interface, 16... LAN. 17... I10 device, 18... Hard disk device, 19... Floppy disk device, 20... Disk interface, 21... Printer, 22... Printer interface, 23... Keyboard, 24. ...Mouse, 25...Interface, 26...FLCD (FLCD display), 26
a... Temperature sensor, 27... FLCD interface, 31... Address bus driver, 32... Control bus driver, 33, 43.4
4... Data bus driver, 34... Sampling counter, 35... Address selector, 36... FIFO (A) memory, 37... FIFO (B) memory, 38... Address counter, 39 ... Synchronous control circuit, 40... Memory controller, 41... Video memory, 42... Driver receiver, Sl, S2... Switch, 50... Selector, 100, 150... Partial rewriting Request circuit, 101, 10
2.105.121.123.125.131107,
137...Request control circuit, 109, 133...Address counter, 200...
Image data synthesis circuit, 201.205...Register, 207...Sub-scanning comparison circuit, 209...Main-scanning counter, 211...Cursor RAM. 213...Logic synthesis circuit.・・・Register, diagram

Claims (1)

[Scope of Claims] 1) A display control device for a display device capable of partially changing the display state of pixels, comprising: a storage means for storing data to be displayed on the display device; and a storage device for displaying the data on the display device. A display control device comprising: composition means for synthesizing data to be synthesized according to the graphic event with respect to data to be displayed at a position specified according to the graphic event. . 2) The display control device according to claim 1, wherein the graphic event is a cursor display, and the data to be combined is cursor data.