JPH0473951A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease parasitic capacitance generated between an arbitrary signal wiring and a semiconductor substrate having the ground potential and to achieve the high speed in a semiconductor device by arranging a dummy wiring which is connected to the signal wiring through a buffer circuit and has the same phase in potential in parallel with the specified signal wiring. CONSTITUTION:A dummy wiring 4 is arranged in parallel with a specified signal wiring 2. The wiring 4 is connected to the signal wiring 2 through a buffer circuit. The wiring 4 has the same potential phase as that of the wiring 2. For example, the signal wiring 2 and the dummy wiring 4 are connected to the output end of a logic circuit 1. The output of the logic circuit 1 is separated through an inverter, and the signals in the same phase are supplied to the signal wiring 2 and the dummy wiring 4 which are provided in parallel. The signal wiring 2 is connected to a logic circuit 3 in the next stage. The end of the dummy wiring 4 is opened. At this time, the dummy wiring 4 is formed between a semiconductor substrate 5 and the signal wiring 2 which is provided on an insulating film 6 that is provided on the semiconductor substrate 5. The signal in the same phase is supplied to the dummy wiring 4 through the insulating film 6. In this way, the potential difference is not generated between the signal wiring 2 and the dummy wiring 4, and the generation of parasitic capacitance is suppressed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

In a conventional semiconductor device, when a logic circuit 1 and a logic circuit 3 are connected by a signal wiring 2 as shown in FIG. 3, an insulating film 6 provided on a semiconductor substrate 5 as shown in FIG. A signal wiring 2 made of metal wiring such as an aluminum layer was connected thereon. At this time, wiring capacitance is parasitic generated between the signal wiring 2 and the ground potential of the semiconductor substrate 5, etc., which causes a delay in the signal transmission speed between logic circuits.

[Problem to be solved by the invention]

The conventional semiconductor device described above has a drawback in that wiring capacitance is parasiticly generated between the signal wiring and the semiconductor substrate having a different potential, which causes a delay in the signal transmission speed and adversely affects speeding up.

[Means to solve the problem]

In the semiconductor device of the present invention, in parallel to the predetermined signal wiring,
A dummy wiring that is electrically in phase with the signal wiring is connected to the signal wiring via a buffer circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a schematic sectional view of one embodiment of the present invention. As shown in FIG. 1, the signal wiring 2 and dummy wiring 4 connected to the output end of the logic circuit 1 and provided in parallel receive in-phase signals obtained by separating the output of the logic circuit 1 with an inverter. The signal wiring 2 is connected to the next stage logic circuit 2, and the end of the dummy wiring 4 is open.

As shown in FIG. 2, signals of the same phase are supplied between the semiconductor substrate 5 and the signal wiring 2 provided on the insulating film 6 provided on the semiconductor substrate 5 through the insulating film 6. By forming the dummy wiring 4, no potential difference occurs between the signal wiring 2 and the dummy wiring 4, and the generation of parasitic capacitance can be suppressed. Therefore, the wiring capacitance between the semiconductor substrate 5 and the signal wiring 2 is reduced, the signal transmission speed is increased, and the speed of the semiconductor device can be increased.

Note that the dummy wiring 4 may be provided so as to concentrically surround the cross section of the signal wiring 2 with an insulating film interposed therebetween.

〔Effect of the invention〕

As explained above, the present invention can connect arbitrary signal wiring and grounding by arranging a dummy wiring that is electrically in phase and connected to a predetermined signal wiring via a buffer circuit in parallel with a predetermined signal wiring. Parasitic capacitance generated between the semiconductor substrate and the semiconductor substrate having a potential can be reduced. This has a great effect on increasing the speed of semiconductor devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic sectional view of an embodiment of the present invention, FIG. 3 is a block diagram showing an example of a conventional semiconductor device, and FIG. 4 is a block diagram showing an example of a conventional semiconductor device. 1 is a cross-sectional view showing an example of a conventional semiconductor device 1. FIG. 1.3...Logic circuit, 2...Signal wiring, 4...
Dummy wiring, 5... semiconductor substrate, 6... insulating film.

Claims (1)

[Claims] 1. A semiconductor device characterized in that a dummy wiring having the same potential phase is arranged in parallel with a predetermined signal wiring and connected to the signal wiring via a buffer circuit.