JPH04742A - semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize high density integration by making a lower side of a second functional block shorter than an upper side of a first functional block in a wiring region corresponding to the number of wirings which are wired and connected from the upper side of the first functional block to the second functional block and an upper region of a lower side of the second functional block. CONSTITUTION:Since an R/L part 1 and an MCU part 2 are not connected directly but connected through a peripheral cell 6, a wiring 5 concentrates to the part of an input and output terminal of the periphery cell 6. The wiring 5 is connected from the R/L part 1 and the MCU part 2 to peripheral cells 6, respectively. The wiring 5 concentrates on a wiring region 4 wherein the R/L part 1, the MCU part 2 and the peripheral cell 6 are approximate. In a region wherein the R/L part 1, the MCU part 2 and the peripheral cell 6 are approximate, a length of a functional block of the R/L part 1 in a direction parallel to a side thereto a functional block of the R/L part 1 and a functional block of the MCU part 2 are adjacent is shorter than a functional block of the MCU part 2; therefore, a space region without wiring inside a wiring region is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit.

[Prior Art] FIG. 3 is a plan view showing a chip layout of a conventional semiconductor integrated circuit. In the figure, ( ) is an R/L (random logic) section, (2) is an MCU section, (3) is a peripheral cell region, and (4) is a wiring region.

FIG. 4 is a partially enlarged view of FIG. 3, showing the connection relationship between the R/L (random logic) section (1), the MCU section (2), and the peripheral cells (6). In the figure, an R/L (random logic) section (1), a peripheral cell (6), an MCU section (
2) and a peripheral cell (6), respectively, and an R/L (random logic) section (1) and an MCU section (2) are connected via the peripheral cell (6).

As shown in Fig. 4, the R/L (random logic) section (
1) and the MCU section (2) are not directly connected, but are connected via the peripheral cell (6), so the peripheral cell (6)
Wiring (5) gathers at the input/output terminal portion of the. R/L (
The wiring (51) is connected from the random logic) section (1) and the MCU section (2) to the peripheral cell (6), respectively, and the R
/L (random 09229 part (1), MCU part (2)
, the wiring area adjacent to the peripheral cell (6) is the wiring (5)
or become dense.

[Issues that invention attempts to solve once and for all]

As shown in Figure 3, the chip layout of a conventional semiconductor integrated circuit is such that the R/L (random logic) section and the MCU section are connected to peripheral cells, respectively. The wiring to be connected is also connected through the 5 peripheral cells, so the peripheral cell's power terminal part, R/L (random logic) part, MCU
If the wiring is densely packed in the wiring area of the adjacent area, the width of the wiring area (4) or the width of the wiring in the R/L (random logic) area, MCU area, or the adjacent wiring area of the peripheral cell. Therefore, there is a problem in that an empty area where no wiring is laid out occurs in the wiring area other than the wiring area adjacent to the R/L (random logic) section, MCU section, or peripheral cells.

This invention was made in order to solve the above-mentioned problems, and aims to eliminate the vacant area that occurs in the wiring area other than the area where the R/L (random logic) section, MCU section, and peripheral cells are adjacent. The present invention aims to increase the R-line density of the wiring region, reduce the overall chip size, and achieve higher integration of semiconductor integrated circuits.

[Means to solve the problem]

In the semiconductor integrated circuit according to the present invention, when laying out the R/L (random logic) section and the MCU section,
/L (Random Logic) part Considering the width of the wiring in the peripheral inter-cell line area of the MCUC, the function of the R/L (Random Logic) part that touches the wiring area where the number of wiring is larger and the width of the wiring is larger. Block R/L (random logic)
The length in the direction perpendicular to the direction in which the MCU section and the MCU section are lined up is made shorter than the length in the same direction of the functional block with the existing MCU section.

[For production]

In the semiconductor integrated circuit according to the present invention, it is possible to eliminate the vacant area that has occurred in the wiring area m, and it is possible to increase the wiring density in the wiring area.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a plan view showing the chip layout of a semiconductor integrated circuit which is an embodiment of the present invention.
L (random logic) part, (2( is MCU part, (3
) is a peripheral cell area, and (4) is a wiring area.

Figure 2 is a partial enlarged plan view of Figure 1, showing the R/L (random logic) section (1), MCU section (2), peripheral cells (6
) is a diagram showing the connection relationship of. In the figure, R/L
(Random logic) section (1) and MCU section (2) are connected via peripheral cells.

As shown in Fig. 2, the R/L (random logic) section (1) and the MCU section (2) are not directly connected and the peripheral cells (
6), the wiring (5) gathers at the input/output terminal portion of the peripheral cell (6). Wiring (5) is connected from the R/L (random logic) section fi+ and the MCU section (2) to the peripheral cell (6), and the R/L
(Random logic) portion (1), MCU portion (2), and wiring region (4) where peripheral cells (6) are close to each other are densely populated with wiring (5).

In Figure 2, the R/L (random logic) section (1
), MCU unit (2), peripheral cells (6), and in the area adjacent to each other, the functional block of the R/L (random logic) unit is /L (Random logic) The length of the functional block in section (1) is shorter than the length of the functional block in MCU section (2), so the free space in the wiring area that is not wired is becomes smaller.

The MClJ section (2) is an existing functional block, and is an R/L (random logic) section t1) of a circuit for a specific application.
can change the functional block size.

Even if the functional block size of the R/L (random logic) section (1) is changed, there is little variation in area. So, R/L (random logic 9 part ill and MCU part (
2) It becomes smaller in the direction perpendicular to the direction in which R/L (
Even if the size of the random logic section (1) and the MCU section (2) increases in the direction in which they are lined up, the area of the entire chip decreases as the free space within the wiring area decreases.

[Effect of the invention 1 As described above, according to the present invention, the wiring within the wiring area can be laid out so as to minimize the free space, so the wiring density within the wiring area can be ,
The overall chip area can be minimized. Another advantage is that a highly integrated semiconductor integrated circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a chip layout of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG.
Figure 1 is a partially enlarged plan view showing the connection relationships among the R/L (random logic) section, MCU section, and peripheral cells; Figure 3 is a plan view showing the chip layout of a conventional semiconductor integrated circuit; Figure 4 is the R/L (Random FIG. 4 is a partially enlarged plan view of FIG. 3 showing a connection relationship among a logic section, an MCU section, and peripheral cells; In the figure, (1) is R/L (random logic car,
(2) is the MCU section, (3) is the peripheral cell area, (4) is the wiring area, (51 is the wiring, and (6) is the peripheral cell. In the figures, the same reference numerals indicate the same or equivalent parts. show.

Claims (1)

[Claims] Consists of a first functional block and a second functional block,
The upper side of the first functional block and the lower side of the second functional block are arranged adjacent to each other with a wiring area in between, and the second functional block and the second function are arranged from the upper side of the first functional block to the lower side of the second functional block. A semiconductor integrated circuit characterized in that the lower side of the second functional block is shorter than the upper side of the first functional block by a wiring area corresponding to the number of wires connected to the area above the lower side of the block.