JPH0474462U - - Google Patents

Info

Publication number
JPH0474462U
JPH0474462U JP1990118177U JP11817790U JPH0474462U JP H0474462 U JPH0474462 U JP H0474462U JP 1990118177 U JP1990118177 U JP 1990118177U JP 11817790 U JP11817790 U JP 11817790U JP H0474462 U JPH0474462 U JP H0474462U
Authority
JP
Japan
Prior art keywords
chip
die pad
solder
utility
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990118177U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990118177U priority Critical patent/JPH0474462U/ja
Publication of JPH0474462U publication Critical patent/JPH0474462U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図はこの考案の一実施例であるICフレー
ムにICチツプをはんだ付けした状態を示す斜視
図、第2図は第1図の−線における断面図、
第3図は従来のICフレームにICチツプをはん
だ付けした状態を示す斜視図、第4図は第3図の
−線における断面図である。 図において、1はダイパツド、1aはダイパツ
ド吊り、1bはダイパツド1の内実際ICチツプ
が載るくぼみを設けた部分、1cはダイパツド1
の内の周辺部分、2はICチツプ、3ははんだ、
3aははんだ不足部分、3bははんだ過剰部分を
示す。なお、図中、同一符号は同一、または相当
部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. ICフレームにおいてダイパツド部のICチツ
    プが載る部分を、そのまわり部分より低くしては
    んだ溜りを設けたことを特徴とするICフレーム
JP1990118177U 1990-11-09 1990-11-09 Pending JPH0474462U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990118177U JPH0474462U (ja) 1990-11-09 1990-11-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990118177U JPH0474462U (ja) 1990-11-09 1990-11-09

Publications (1)

Publication Number Publication Date
JPH0474462U true JPH0474462U (ja) 1992-06-30

Family

ID=31866081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990118177U Pending JPH0474462U (ja) 1990-11-09 1990-11-09

Country Status (1)

Country Link
JP (1) JPH0474462U (ja)

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