JPH0474949B2 - - Google Patents
Info
- Publication number
- JPH0474949B2 JPH0474949B2 JP58035658A JP3565883A JPH0474949B2 JP H0474949 B2 JPH0474949 B2 JP H0474949B2 JP 58035658 A JP58035658 A JP 58035658A JP 3565883 A JP3565883 A JP 3565883A JP H0474949 B2 JPH0474949 B2 JP H0474949B2
- Authority
- JP
- Japan
- Prior art keywords
- phase
- circuit
- signal
- phase difference
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 54
- 238000006243 chemical reaction Methods 0.000 claims description 21
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 230000010355 oscillation Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- NCGICGYLBXGBGN-UHFFFAOYSA-N 3-morpholin-4-yl-1-oxa-3-azonia-2-azanidacyclopent-3-en-5-imine;hydrochloride Chemical compound Cl.[N-]1OC(=N)C=[N+]1N1CCOCC1 NCGICGYLBXGBGN-UHFFFAOYSA-N 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010587 phase diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Protection Of Static Devices (AREA)
- Direct Current Feeding And Distribution (AREA)
- Rectifiers (AREA)
- Power Conversion In General (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、直流送電等に使用される電力変換装
置の位相連続比較形同期信号検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase continuous comparison type synchronization signal detection circuit for a power conversion device used for DC power transmission or the like.
第1図は直流送電システムの構成を示すブロツ
ク線図である。1−1は送電側三相交流母線、1
−2は受電側三相交流母線であり、この母線1−
1,1−2間には平滑リアクトル3−1,3−2
を接続した直流線路2が配設さている。また交流
母線1−1,1−2と直流線路2との間には、そ
れぞれ変換器用圧器4−1,4−2及び電力変換
装置5−1,5−2が設けられる。各電力変換装
置5−1,5−2は直並列接続されたサイリスタ
素子で構成され、一方の順変換装置5−1は交流
を直流に、他方の逆変換装置5−2は直流を交流
にそれぞれ電力変換する。そしてこの変換装置5
−1,5−2の導通角を制御するために、計器用
変圧器6−1,6−2、同期信号検出回路7−
1,7−2及び位相制御回路8−1,8−2がそ
れぞれ設けられている。そして各同期信号検出回
路7−1,7−2では計器用変換器6−1,6−
2から得られる交流同期信号に追従して該同期信
号を検出して各位相制御回路8−1,8−2に与
える。するとこの位相制御回路8−1,8−2で
は、前記同期信号を基準信号として、図示されて
いない他の制御回路からの制御信号により点弧パ
ルスを発生し、各変換装置5−1,5−2間のサ
イリスタ等へ与える。これにより、例えば、順変
換装置5−1では送電側交流母線1−1から与え
られる三相交流を直流に変換する際に定電流制御
を行ない直流線路2に供給する。一方、受電側の
逆変換装置5−2では直流線路2を介して送られ
てきた直流を三相交流に変換する際に定電圧制御
を行ない受電側交流母線1−2に与える。
FIG. 1 is a block diagram showing the configuration of a DC power transmission system. 1-1 is the power transmission side three-phase AC bus, 1
-2 is a three-phase AC bus on the receiving side, and this bus 1-
Smooth reactor 3-1, 3-2 between 1, 1-2
A DC line 2 is provided which connects the . Further, converter pressure vessels 4-1, 4-2 and power converters 5-1, 5-2 are provided between the AC buses 1-1, 1-2 and the DC line 2, respectively. Each power conversion device 5-1, 5-2 is composed of thyristor elements connected in series and parallel, one forward conversion device 5-1 converts AC to DC, and the other inverse conversion device 5-2 converts DC to AC. Each converts power. And this conversion device 5
-1, 5-2, the instrument transformers 6-1, 6-2, the synchronous signal detection circuit 7-
1 and 7-2 and phase control circuits 8-1 and 8-2, respectively. In each synchronous signal detection circuit 7-1, 7-2, an instrument converter 6-1, 6-
2, the synchronizing signal is detected and applied to each phase control circuit 8-1, 8-2. Then, in the phase control circuits 8-1 and 8-2, using the synchronization signal as a reference signal, a firing pulse is generated by a control signal from another control circuit (not shown), and each conversion device 5-1, 5 −2 to the thyristor, etc. Thereby, for example, the forward converter 5-1 performs constant current control when converting three-phase alternating current given from the power transmission side AC bus 1-1 into direct current, and supplies the direct current to the direct current line 2. On the other hand, the inverter 5-2 on the power receiving side performs constant voltage control when converting the DC sent via the DC line 2 into three-phase AC, and applies it to the AC bus 1-2 on the power receiving side.
このような直流送電システムにおける前記同期
信号検出回路7−1,7−2として、従来各種の
回路方式が採用されているが、近年デイジタル技
術の進歩により位相連続比較形の同期信号検出回
路が採用されるに至つた。 Conventionally, various circuit systems have been adopted as the synchronization signal detection circuits 7-1 and 7-2 in such a DC power transmission system, but in recent years, with the advancement of digital technology, a phase continuous comparison type synchronization signal detection circuit has been adopted. It has come to be.
第2図は、従来の位相連続比較形同期信号検出
回路7−1,7−2の構成を示すブロツク線図で
ある。図において、10は3層交流同期信号を直
交する2相に変換する3相−2相変換回路であ
り、この3相−2相変換回路10の出力信号は位
相差検出演算回路11に与えられる。該位相差検
出演算回路11は、3相−2相変換回路10の出
力信号と、フイードバツク信号を発生する正弦波
発生回路12及び余弦波発生回路13の出力信号
とを入力して位相差を求め、ループフイルタ14
を介して電圧制御発振器15に与える。電圧制御
発振器15はループフイルタ14の出力信号によ
り制御されて所定周波数のパルス信号を出力し、
カウンタ16に与える。すると該カウンタ16は
前記パルス信号を計数して同期信号を出力し、位
相制御回路8−1,8−2と前記正弦波発生回路
12及び余弦波発生回路13に与える。 FIG. 2 is a block diagram showing the configuration of conventional phase continuous comparison type synchronization signal detection circuits 7-1 and 7-2. In the figure, 10 is a 3-phase to 2-phase conversion circuit that converts the 3-layer AC synchronizing signal into two orthogonal phases, and the output signal of this 3-phase to 2-phase conversion circuit 10 is given to a phase difference detection calculation circuit 11. . The phase difference detection calculation circuit 11 inputs the output signal of the three-phase to two-phase conversion circuit 10 and the output signals of the sine wave generation circuit 12 and cosine wave generation circuit 13 that generate feedback signals, and calculates the phase difference. , loop filter 14
It is applied to the voltage controlled oscillator 15 via. The voltage controlled oscillator 15 is controlled by the output signal of the loop filter 14 and outputs a pulse signal of a predetermined frequency.
It is given to the counter 16. Then, the counter 16 counts the pulse signals and outputs a synchronizing signal, which is applied to the phase control circuits 8-1, 8-2, the sine wave generating circuit 12, and the cosine wave generating circuit 13.
次に、このように構成される同期信号検出回路
7−1,7−2の動作について説明する。いま、
3相−2相変換回路10の出力電圧の瞬時値を
V1d、V1g、その振幅(最大値)をT1、位相をθ1
とし、カウンタ16を介して得られるフイードバ
ツク信号である正弦波発生回路12の出力をVfg、
余弦波発生回路13の出力をVfdとし、検出位相
をθとすれば、次式が成り立つ。 Next, the operation of the synchronizing signal detection circuits 7-1 and 7-2 configured as described above will be explained. now,
The instantaneous value of the output voltage of the 3-phase to 2-phase conversion circuit 10 is
V 1d , V 1g , their amplitude (maximum value) is T 1 , phase is θ 1
The output of the sine wave generating circuit 12, which is the feedback signal obtained via the counter 16, is V fg ,
If the output of the cosine wave generating circuit 13 is V fd and the detected phase is θ, then the following equation holds true.
V1d=V1・cosθ1 ……(1)
V1g=V1・sinθ1 ……(2)
Vfd=cosθ ……(3)
Vfg=sinθ ……(4)
従つて、位相差△θ=θ1−θは、位相差検出演
算回路11により次式の演算を行なうことにより
求められる。 V 1d = V 1・cosθ 1 …(1) V 1g = V 1・sinθ 1 …(2) V fd = cosθ …(3) V fg = sinθ …(4) Therefore, the phase difference △ θ=θ 1 -θ is obtained by calculating the following equation using the phase difference detection calculation circuit 11.
△θ=sin-1Vfd・V1g−Vfg・V1d/V1 ……(5)
但し、最大値(すなわち絶対値)V1は次式の
ようになる。△θ=sin -1 V fd・V 1g −V fg・V 1d /V 1 ...(5) However, the maximum value (that is, absolute value) V 1 is as shown in the following equation.
V1=1d 2+1g 2 ……(6)
このように位相差検出演算回路11により求め
られた位相差△θは、ループフイルタ14により
誤差増幅され、その出力信号により電圧制御発振
器15が制御され、カウンタ16を介して該位相
差△θが零になるようフイードバツク制御され
る。V 1 = 1d 2 + 1g 2 ...(6) The phase difference △θ thus obtained by the phase difference detection calculation circuit 11 is error amplified by the loop filter 14, and the voltage controlled oscillator 15 is controlled by its output signal. The phase difference Δθ is feedback-controlled via the counter 16 so that the phase difference Δθ becomes zero.
しかしながら、上記位相連続比較形の同期信号
検出回路7−1,7−2にあつては、例えば、第
1図に示す交流母線1−1の電圧が落雷等により
大幅に低下すると、第2図中の3相−2相変換回
路10の入力信号である3相の交流同期信号R,
S,Tが大幅に低下するので、該同期信号検出回
路7−1,7−2が同期はずれを引き起こし、そ
の結果保護操作ができないという不具合があつ
た。
However, in the phase continuous comparison type synchronizing signal detection circuits 7-1 and 7-2, if the voltage of the AC bus 1-1 shown in FIG. A three-phase AC synchronizing signal R, which is an input signal of the three-phase to two-phase conversion circuit 10 in the middle,
Since S and T were significantly reduced, the synchronization signal detection circuits 7-1 and 7-2 caused a loss of synchronization, resulting in a problem that protection operations could not be performed.
この不具合を除去する手段として、ループフイ
ルタ14のゲインを小さくする等の方法が考えら
れる。すなわち、この方法は、同期はずれを引き
起しにくいようにする方法であるが、この方法を
採用すると、一旦同期はずれが引き起されると再
度同期がとれるまでに長時間かかるというう不具
合が生ずる。このことは、従来の同期信号検出回
路に比較して位相連続比較形の同期信号検出回路
の利点、すなわち位相を常に比較してループフイ
ルタ14の比例定数を大きくし、フイードバツク
系のゲインを大きくすることにより高速に同期信
号の検出を行なうことができるという利点を失な
うことになるので、好ましくない。 As a means to eliminate this problem, a method such as reducing the gain of the loop filter 14 can be considered. In other words, this method is a method that makes it difficult for synchronization to occur, but when this method is adopted, a problem arises in that once synchronization occurs, it takes a long time to regain synchronization. . This is an advantage of the continuous phase comparison type synchronizing signal detecting circuit compared to the conventional synchronizing signal detecting circuit, that is, by constantly comparing the phases, the proportionality constant of the loop filter 14 is increased, and the gain of the feedback system is increased. This is not preferable because the advantage of being able to detect the synchronization signal at high speed is lost.
本発明は、以上のような従来技術の欠点に鑑み
てなされたもので、三相交流電圧が大幅に低下し
ても同期はずれが起らず、しかも同期信号の検出
を高速に行なえる電力変換装置の位相連続比較形
同期信号検出回路を提供することを目的とする。
The present invention has been made in view of the above-mentioned shortcomings of the conventional technology, and provides a power conversion system that does not cause synchronization even when the three-phase AC voltage significantly decreases, and that can detect synchronization signals at high speed. It is an object of the present invention to provide a phase continuous comparison type synchronization signal detection circuit for a device.
この目的を達成するために、本発明では、三相
交流信号が所定値以下に低下した場合には、3相
−2相変換回路の出力信号の代わりに、フイード
バツク正弦波発生回路及びフイードバツク余弦波
発生回路の出力信号を位相差検出演算回路へ与え
るようにしている。
To achieve this objective, in the present invention, when the three-phase AC signal drops below a predetermined value, a feedback sine wave generator and a feedback cosine wave generator are used instead of the output signal of the three-phase to two-phase conversion circuit. The output signal of the generation circuit is supplied to the phase difference detection calculation circuit.
以下、添付図面を参照しつつ本発明の実施例を
説明する。
Embodiments of the present invention will be described below with reference to the accompanying drawings.
第3図はこの実施例に係る位相連続比較形同期
信号検出回路の構成を示すブロツク線図であり、
前記第2図と同一要素は同一符号が付されてい
る。そしてこの同期信号検出回路が第2図の回路
と異なる点は、レベル検出回路20とこの検出回
路20により切換えられる切換スイツチ21,2
2を設けた点にある。 FIG. 3 is a block diagram showing the configuration of the phase continuous comparison type synchronization signal detection circuit according to this embodiment.
The same elements as in FIG. 2 are given the same reference numerals. The difference between this synchronizing signal detection circuit and the circuit shown in FIG.
2 was established.
そしてレベル検出回路20は、3相交流同期信
号R,S,Tの電圧が所定値以下に低下したこと
を検出するもので、該レベル検出回路20の出力
信号は、通常はレベル“0”であるが、3相交流
同期信号R,S,Tが所定値以下に電圧低下する
とレベル“1”となり、該出力信号を各切換スイ
ツチ21,22に与える。切換スイツチ21,2
2はスイツチングトランジスタ等で構成され、前
記レベル検出回路20の出力信号に基づいて切換
えられるもので、3相−2相変換回路10と位相
差検出演算回路11との間に設けられている。そ
して各切換スイツチ21,22はレベル検出回路
20の出力信号がレベル“0”のときは、3相・
2相変換回路10の出力信号を位相差検出演算回
路11へ与え、一方、レベル検出回路20の出力
信号がレベル“1”のときは、切換えられてフイ
ードバツク正弦波発生回路12及びフイードバツ
ク余弦波発生回路13の出力信号を位相差検出演
算回路11へ与える。 The level detection circuit 20 detects when the voltages of the three-phase AC synchronizing signals R, S, and T have fallen below a predetermined value, and the output signal of the level detection circuit 20 is normally at level "0". However, when the voltage of the three-phase AC synchronizing signals R, S, T drops below a predetermined value, the level becomes "1", and the output signal is given to each changeover switch 21, 22. Changeover switch 21, 2
Reference numeral 2 is composed of a switching transistor or the like, which is switched based on the output signal of the level detection circuit 20, and is provided between the three-phase to two-phase conversion circuit 10 and the phase difference detection calculation circuit 11. When the output signal of the level detection circuit 20 is at level "0", each changeover switch 21, 22 is set to 3-phase.
The output signal of the two-phase conversion circuit 10 is applied to the phase difference detection calculation circuit 11. On the other hand, when the output signal of the level detection circuit 20 is at level "1", it is switched to the feedback sine wave generation circuit 12 and the feedback cosine wave generation circuit. The output signal of the circuit 13 is given to the phase difference detection calculation circuit 11.
次に、このように構成される位相連続比較形同
期信号検出回路の動作について説明する。 Next, the operation of the phase continuous comparison type synchronization signal detection circuit configured as described above will be explained.
さて、3相−2相変換回路10の入力信号であ
る3相交流同期信号R,S,Tが、正常な値また
は所定値まで低下しない場合には、レベル検出回
路20の出力信号が“0”レベルであるため、各
切換スイツチ21,22は3相−2相変換回路1
0の出力信号を選択して位相差検出演算回路11
へ与える。従つてこの状態では、従来の位相連続
比較同期信号検出回路の動作と同様の動作、すな
わち位相差検出演算回路11で位相差△θが求め
られ該位相差△θがループフイルタ14、電圧制
御発振器15、カウンタ6、正弦波発生回路12
及び余弦波発生回路13を介して零になるように
フイードバツク制御され、3相交流同期信号R,
S,Tに追従してその検出が行なわれる。 Now, if the three-phase AC synchronizing signals R, S, T, which are the input signals of the three-phase to two-phase conversion circuit 10, do not decrease to a normal value or a predetermined value, the output signal of the level detection circuit 20 will be "0". ” level, each changeover switch 21, 22 is connected to the 3-phase to 2-phase conversion circuit 1.
The phase difference detection calculation circuit 11 selects the output signal of 0.
give to Therefore, in this state, the operation is similar to that of the conventional phase continuous comparison synchronization signal detection circuit, that is, the phase difference Δθ is determined by the phase difference detection calculation circuit 11, and the phase difference Δθ is transmitted to the loop filter 14 and the voltage controlled oscillator. 15, counter 6, sine wave generation circuit 12
The three-phase AC synchronizing signals R,
Detection is performed following S and T.
ここで、3相の交流同期信号R,S,Tが落雷
等により大幅に低下した場合を考える。この状態
のままで放置しておくと、前述したごとく位相連
続比較形同期信号検出回路は同期はずれを引き起
す。しかしながら、第3図に示すようにループフ
イルタ14が設けられているため、3相の交流同
期信号が大幅に低下した時点で、すぐに位相連続
比較形同期信号検出回路が同期はずれを引き起す
ことはない。すなわち、仮に3相交流同期信号
R,S,Tが零となつても、ある時間はフイード
バツク正弦波発生回路12及びフイードバツク余
弦波発生回路13が出力信号を発生している。そ
こでレベル検出回路20によつて3相の交流同期
信号の大幅な低下を検出し、この検出信号に基づ
いて切換スイツチ21,22を切換え、フイード
バツク正弦波発生回路12及び余弦波発生回路1
3の出力信号を位相差検出演算回路11へ与える
ようにすれば、安定な動作を続け、同期はずれを
引き起こすことがない。 Here, consider a case where the three-phase AC synchronizing signals R, S, and T are significantly reduced due to a lightning strike or the like. If this state is left as it is, the phase continuous comparison type synchronization signal detection circuit will lose synchronization as described above. However, since the loop filter 14 is provided as shown in FIG. 3, the phase continuous comparison type synchronization signal detection circuit immediately causes synchronization to occur when the three-phase AC synchronization signal drops significantly. There isn't. That is, even if the three-phase AC synchronizing signals R, S, and T become zero, the feedback sine wave generating circuit 12 and the feedback cosine wave generating circuit 13 continue to generate output signals for a certain period of time. Therefore, the level detection circuit 20 detects a significant drop in the three-phase AC synchronizing signal, switches the changeover switches 21 and 22 based on this detection signal, and controls the feedback sine wave generation circuit 12 and cosine wave generation circuit 1.
If the output signal No. 3 is applied to the phase difference detection calculation circuit 11, stable operation will continue and no synchronization will occur.
なお、上記実施例において、レベル検出回路2
0はアナログ信号を出力するように構成し、この
出力信号に基づいて切換スイツチ21,22を切
換えるようにしても、上記実施例と同様の作用・
効果を奏する。 Note that in the above embodiment, the level detection circuit 2
Even if 0 is configured to output an analog signal and the changeover switches 21 and 22 are switched based on this output signal, the same effects and effects as in the above embodiment can be obtained.
be effective.
以上述べたように、本発明によれば、従来の位
相連続比較形同期信号検出回路に、レベル検出回
路と切換スイツチを付加し、3相の交流同期信号
が所定値以下に低下したときにこれをレベル検出
回路で検出し、この検出信号に基づいて3相−2
相交流回路の出力信号を切換えフイードバツク正
弦波発生回路及びフイードバツク余弦波発生回路
の出力信号を位相差検出演算回路11へ与えるよ
うにしたので、交流電圧低下時にも同期はずれが
起らず、かつ高速に同期がかるという従来の位相
連続比較形同期信号検出回路の利点をも失うこと
がない、簡易的確な同期信号検出回路を提供でき
る。
As described above, according to the present invention, a level detection circuit and a changeover switch are added to the conventional phase continuous comparison type synchronization signal detection circuit, and when the three-phase AC synchronization signal falls below a predetermined value, is detected by the level detection circuit, and based on this detection signal, the 3-phase - 2
Since the output signals of the phase AC circuit are switched and the output signals of the feedback sine wave generation circuit and the feedback cosine wave generation circuit are fed to the phase difference detection calculation circuit 11, synchronization does not occur even when the AC voltage drops, and high speed operation can be achieved. It is possible to provide a simple and accurate synchronization signal detection circuit that does not lose the advantage of the conventional phase continuous comparison type synchronization signal detection circuit that synchronization is achieved.
第1図は直流送電システムの説明図、第2図は
第1図中に設けられた従来の位相連続比較形同期
信号検出回路のブロツク線図、第3図は本発明の
実施例に係る位相連続比較形同期信号検出回路の
ブロツク線図である。
1−1,1−2……交流母線、2……直流線
路、5−1,5−2……電力変換装置、6−1,
6−2……計器用変圧器、7−1,7−2……同
期信号検出回路、8−1,8−2……位相制御回
路、10……3相−2相変換回路、11……位相
差検出演算回路、12……正弦波発生回路、13
……余弦波発生回路、14……ループフイルタ、
15……電圧制御発振器、16……カウンタ、2
0……レベル検出回路、21,22……切換スイ
ツチ、3−1,3−2……平滑りアクトル、4−
1,4−2……変換器用変圧器。
FIG. 1 is an explanatory diagram of a DC power transmission system, FIG. 2 is a block diagram of a conventional phase continuous comparison type synchronous signal detection circuit provided in FIG. 1, and FIG. 3 is a phase diagram according to an embodiment of the present invention. FIG. 2 is a block diagram of a continuous comparison type synchronization signal detection circuit. 1-1, 1-2... AC bus, 2... DC line, 5-1, 5-2... Power converter, 6-1,
6-2... Instrument transformer, 7-1, 7-2... Synchronous signal detection circuit, 8-1, 8-2... Phase control circuit, 10... 3-phase to 2-phase conversion circuit, 11... ...Phase difference detection calculation circuit, 12...Sine wave generation circuit, 13
... Cosine wave generation circuit, 14 ... Loop filter,
15... Voltage controlled oscillator, 16... Counter, 2
0... Level detection circuit, 21, 22... Changeover switch, 3-1, 3-2... Smooth sliding actuor, 4-
1, 4-2...Transformer for converter.
Claims (1)
る3相−2相変換回路と、3相−2相変換回路の
出力信号とフイードバツク正弦波発生回路及びフ
イードバツク余弦波発生回路の出力信号とに基づ
いて位相差を求める位相差検出演算回路と、位相
差検出演算回路からループフイルタを介して入力
される位相差信号により発振制御されて同期信号
を出力する電圧制御発振器とを具備した位相連続
比較形同期信号検出回路において、 前記3相の交流同期信号が所定値以下に低下し
たことを検出するレベル検出回路と、このレベル
検出回路の検出信号に基づいて前記3相−2相変
換回路の出力信号をしゃ断して前記フイードバツ
ク正弦波発生回路及びフイードバツク余弦波発生
回路の出力信号を前記位相差検出演算回路へ与え
る切換スイツチとを具備したことを特徴とする位
相連続比較形同期信号検出回路。[Claims] 1. A 3-phase to 2-phase conversion circuit that converts a 3-phase AC synchronous signal to two orthogonal phases, an output signal of the 3-phase to 2-phase conversion circuit, a feedback sine wave generation circuit, and a feedback cosine wave A phase difference detection calculation circuit that calculates the phase difference based on the output signal of the generation circuit, and a voltage controlled oscillator that outputs a synchronization signal by controlling oscillation by the phase difference signal input from the phase difference detection calculation circuit via a loop filter. A level detection circuit for detecting that the three-phase AC synchronization signal has fallen below a predetermined value; - a changeover switch that cuts off the output signal of the two-phase conversion circuit and supplies the output signal of the feedback sine wave generation circuit and the feedback cosine wave generation circuit to the phase difference detection calculation circuit; Synchronous signal detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035658A JPS59162767A (en) | 1983-03-04 | 1983-03-04 | Phase continuous comparison type synchronizing signal detecting circuit of power converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035658A JPS59162767A (en) | 1983-03-04 | 1983-03-04 | Phase continuous comparison type synchronizing signal detecting circuit of power converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59162767A JPS59162767A (en) | 1984-09-13 |
| JPH0474949B2 true JPH0474949B2 (en) | 1992-11-27 |
Family
ID=12447967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58035658A Granted JPS59162767A (en) | 1983-03-04 | 1983-03-04 | Phase continuous comparison type synchronizing signal detecting circuit of power converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59162767A (en) |
-
1983
- 1983-03-04 JP JP58035658A patent/JPS59162767A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59162767A (en) | 1984-09-13 |
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