JPH0475034A - Active matrix display device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce an insulation defect between gate bus wiring and source bus wiring and an insulating defect between an electrdddoe for additional capacity and a picture element electrode by providing an anode oxide film on both flanks of the gate bus wiring and electrode for additional capacity. CONSTITUTION:This display device is equipped with the picture element electrode 10 formed on an insulating substrate 12, a TFT 20 which is connected to the picture element electrode 10, the gate bus wiring 20 which is connected to the TFT 20, and the electre 3 for additional capacity which faces the picture element electrode 10, and part of the gate bus wiring 2 functions as the gate electrode of the TFT 20. No anode oxide film is provided on the gate bus wiring 2 and the anode oxide films 4a and 4a are provided only on both flanks of the gate bus wiring 2. Similarly, no anode oxide film is proivded on the electrode 3 for additional capacity and the anode oxide films 4b and 4b are provided only on both flanks of the electroe 3 for additional capacity. Consequently, the insulation, defect between the gate bus wiring 2 and electrode 3 for additional capacity and the insulation defect between teh electroe 3 for additional capacity and picture element electrode 10 are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix display device having thin film transistors (hereinafter referred to as rTFTs) as switching elements.

(Prior Art) FIG. 3(a) shows a cross-sectional view of an active matrix substrate used in a conventional active matrix display device. This active matrix substrate includes a picture element electrode 10 formed on an insulating substrate 12 made of glass, a TPT 20 connected to the picture element electrode 10, a gate bus wiring 2 connected to the TPT 20, and a picture element electrode 10 formed on an insulating substrate 12 made of glass. It has an additional capacitance electrode 3 that is coupled to the electrode 3. FIG. 3(b) shows a cross-sectional view taken along one source bus wiring at the intersection of the gate bus wiring 2 and the source bus wiring 19 of the substrate of FIG. 3(a). The active matrix substrate shown in FIGS. 3(a) and 3(1)) will be explained according to the manufacturing process. A base foot film 1 made of Ta205 with a thickness of 1000 to 4000 is deposited on the entire surface of an insulating substrate 12 made of a glass plate by a sputtering method, and then a base foot film 1 made of Ta205 with a thickness of 2000 to 4000 is deposited on the base coat film 1 by a sputtering method as well. 400
A Ta metal film with a thickness of 0 is deposited. By patterning this Ta metal film, gate bus wiring 2 and additional capacitance electrode 3 are formed. A part of the gate bus wiring 2 functions as a gate electrode of a TPT 20 that will be formed later.

Next, the surfaces of the gate bus wiring 2 and the additional capacitance electrode 3 are anodized, and about half of the film thickness of the gate bus wiring 2 and the additional capacitance electrode 3 is covered with a Ta205 anodic oxide film 4.
a and 4b. The anodic oxide film 4a is provided to prevent insulation failure from occurring between the gate bus line 2 and the source bus line 9 intersecting with it in a non-conductive state. Further, the anodic oxide film 4b is provided to prevent insulation defects from occurring between the additional capacitance electrode 3, the source bus wiring 19, and the picture element electrode 10. Next, 100%
A gate insulating film 5 made of SiN having a thickness of 0 to 5000 nm is formed by plasma CVD. Furthermore, the substrate 1
2, an intrinsic semiconductor amorphous silicon (hereinafter referred to as RA-3I(J)J) layer with a thickness of 100 to 300 A, and a SiN layer with a thickness of 1000 to 5000 A,
The layers are sequentially stacked, and the 5jNx layer is patterned by photolithography and etching to form the protective insulating film 7a and the second protective film 7C. The protective insulating film 7a is a-3i(i) located below the protective insulating film 7a.
This layer is provided to protect the portion that will become the semiconductor layer 6 from the etchant.

Next, 100-Zo is applied to the entire surface of the a-3i(i) layer, the protective insulating film 7a, and the second protective film 7C.

An n0 type a-3i layer doped with P (phosphorus) with a thickness of
i) layer and the n+ type a-3i layer are simultaneously patterned to form the semiconductor layer 6 and the protective film 6c of the membrane 1, as well as the contact layers 8a, 8b and the third protective film 8c.

Next, a Ti gold scrap layer is deposited on the entire surface of the substrate 12, and the Ti gold scrap layer is patterned to form the source bus wiring 19, the source electrode 9a, and the drain electrode 9b. Through the above steps, the TFT 20 is completed. Furthermore, I.T.
50 consisting of ○ (Indium Tin Oxide)
After depositing a transparent conductive film with a thickness of 0 to 3000 nm, this is patterned by photolithography and etching to form a picture element electrode IO. The picture element electrode 10 is electrically connected to the drain electrode 9b of the TFT 20. Further, the picture element electrode 10 also extends over the additional capacitor electrode 3, and the picture element electrode 10 and the additional capacitor electrode 3
The additional window fi21 is configured by the above.

The aforementioned anodic oxide film 4b and gate electrode 5 are sandwiched between the picture element electrode 10 and the additional capacitance electrode 3.

As shown in FIG. 3(b), on the gate bus line 2 at the intersection of the gate bus line 2 and the source bus line 19, there is an anodic oxide film 4a, a gate insulating film 5, and a first protective film. 6c, a second protective film 7c, and a third protective film 8c are formed. This five-layer protective film prevents poor insulation between the gate bus wiring 2 and the source bus wiring 19. At the intersection between the additional capacitor electrode 3 and the source bus wiring 19, a five-layer anodic oxide film 4 similar to that shown in FIG. 3(b) is formed.
b. A gate insulating film 5 and protective films 6c, 7c, and 8c are formed.

(Problem to be solved by the invention) In such a conventional active matrix display device,
In order to prevent poor insulation between the gate bus wiring 2 and the additional capacitance electrode 3 and the source bus wiring 19, and to prevent poor insulation between the additional capacitance electrode 3 and the pixel electrode 10, Anodic oxide films 4a and 4b are provided on the bus wiring 2 and the additional capacitance electrode 3, respectively. However, about half the layer thickness of the Ta metal layer formed as the gate bus wiring 2 and the additional capacitance electrode 3 is made of non-conductive Ta.
205, the portions of the gate bus wiring 2 and the additional capacitance electrode 3 are reduced. Therefore, the resistance of the gate bus wiring 2 and the additional capacitance electrode 3 increases.

In order to avoid such an increase in resistance, the gate bus wiring 2
It is also conceivable to increase the width or layer thickness of the additional capacitance electrode 3. However, when the widths of the gate bus wiring 2 and the additional capacitance electrodes 3 are increased, there is a problem that the aperture ratio, that is, the ratio of the total area of the picture element electrodes 10 contributing to display to the area of the entire display screen decreases. . Also, gate/
When the layer thicknesses of the zH bus line 2 and the additional capacitance electrode 3 are increased, there is a problem that the source bus line 19 that crosses the step between the gate bus line 2 and the additional capacitance electrode 3 is more likely to be disconnected. Furthermore, there is a problem that the source electrode 9a is likely to break at the portion of the XS bus line 2 that functions as the gate electrode.

When anodic oxidation is performed, the layer thickness of the gate bus wiring 2 and the anodic oxide film 4a, and the layer thickness of the additional capacitance electrode 3 and the anodic oxide film 4b are changed.
The layer thickness is approximately 1.5 times that of the gate wiring 2 and the additional capacitance electrode 3 before anodizing, so that disconnection of the source bus wiring 19 and disconnection of the source electrode 9a may occur. becomes even more likely to occur.

Furthermore, when the anodic oxide film 4b is provided, the distance between the additional capacitance electrode 3 and the picture element electrode 10 increases, so the additional capacitance 21
In order to fully utilize the function of retaining the video signal of
It is necessary to increase the area of the additional capacitance electrode 3. As the area of the additional capacitance electrode 3 increases, the aperture ratio of the display screen decreases, so measures such as using a powerful backlight are required to maintain display quality. However, making the backlight stronger is not preferable because it leads to deterioration of the characteristics and shortening of the life of the TFT 20.

The present invention solves these problems, and an object of the present invention is to solve poor insulation between gate bus wiring and additional capacitance electrodes and source bus wiring, and to solve poor insulation between additional capacitance electrodes and pixel electrodes. An object of the present invention is to provide an active matrix display device which can reduce the occurrence of insulation defects between sources, and which does not cause disconnection of source bus wiring and does not reduce the aperture ratio. Another object of the present invention is to provide a manufacturing method that can easily manufacture such an active matrix display device.

(Means for Solving the Problems) The active matrix display device of the present invention includes a picture element electrode formed on an insulating substrate, a thin film transistor connected to the picture element electrode, and a gate bus connected to the thin film transistor. An active matrix display device having wiring, in which an anodic oxide film is formed on both sides of the gate bus wiring, thereby achieving the above object.

Further, the active matrix display device of the present invention is an active matrix display device having a picture element electrode formed on an insulating substrate and an electrode for additional capacitance opposite to the picture element electrode, the active matrix display device comprising: An anodic oxide film is formed on both sides of the electrode, thereby achieving the above object.

The method for manufacturing an active matrix display device of the present invention includes:
A step of forming a gate bus wiring on an insulating substrate, a step of applying a photoresist to the entire surface of the substrate, and a step of exposing the back side of the substrate to form a photoresist on the upper surface of the gate bus wiring. and a step of forming an anodic oxide film on both sides of the gate bus wiring, thereby achieving the above object.

Further, the method for manufacturing an active matrix display device of the present invention includes a step of forming an electrode for additional capacitance on an insulating substrate, a step of applying a photoresist to the entire surface of the substrate,
The method includes the steps of forming a photoresist on the upper surface of the additional capacitance electrode by exposing the back surface of the substrate, and forming an anodic oxide film on both sides of the additional capacitance electrode. This achieves the above objective.

(Function) In the active matrix display device of the present invention, an anodic oxide film is formed only on both sides of the gate bus wiring and the additional capacitance electrode. Poor insulation between the source bus wiring and gate bus wiring and additional capacitance electrodes, and poor insulation between the additional capacitance electrodes and pixel electrodes, is caused by the shoulder portions on both sides of the gate bus wiring and additional capacitance electrodes. The majority of cases occur in

Therefore, if anodic oxide films are formed on both sides of the gate bus wiring and the additional capacitance electrode as in the present invention, the above-mentioned insulation defects can be prevented. In addition, since anodized a is not formed on the upper surfaces of the gate bus wiring and the additional capacitance electrodes, the source bus wiring may be disconnected at the intersections between the gate bus wiring and the additional capacitance electrodes and the source bus wiring. do not have. Furthermore, since the distance between the additional capacitor electrode and the picture element electrode can be set small, the width of the additional capacitor electrode can be reduced. Therefore, a display screen with a large aperture ratio can be obtained.

The active matrix display device of the present invention can be manufactured by the following manufacturing method. First, a resist is formed in a self-aligned manner on the upper surfaces of the gate bus wiring and the additional capacitance electrode by exposure from the back side. When anodic oxidation is performed using this resist, an anodic oxide film is formed only on both sides of the gate bus wiring and the additional capacitance electrode. Next, the resist is removed and the active matrix display device of the present invention is obtained through normal steps. According to such a manufacturing method, the upper surfaces of the gate bus wiring and the additional capacitance electrode are not anodized. Therefore, although the gate bus wiring and the additional capacitance electrode have a large layer thickness and have the same width as the gate bus wiring and the additional capacitance electrode manufactured in the conventional example, It can have low resistance.

(Example) Examples of the present invention will be described below. Figure 1(a)
2 shows a cross-sectional view of an active matrix substrate used in an example of the active matrix display device of this embodiment. The active matrix substrate shown in FIG. 1(a) includes a picture element electrode 10 formed on an insulating substrate 12 made of glass, a TFT 20 connected to the picture element electrode 10, and a TFT 20 connected to the picture element electrode 10.
It has a gate bus wiring 2 connected to the pixel electrode 10, and an additional capacitance electrode 3 facing the picture element electrode 10. A part of the gate bus wiring 2 functions as a gate electrode of the TFT 20. In this embodiment, no anodic oxide film is provided on the gate bus wiring 2, and anodic oxide films 4a, 4a are provided only on both sides of the gate bus wiring 2. Similarly, no anodic oxide film is provided on the additional capacitor electrode 3, and anodic oxide films 4b, 4b are provided only on both sides of the additional capacitor electrode 3.

Figure 1(b) shows the gate bus wiring 2 of the board in Figure 1(a).
A cross-sectional view along the source bus wiring 19 at the intersection between the source bus wiring 19 and the source bus wiring 19 is shown.

This example will be explained according to the manufacturing process. A base coat film 1 made of Ta2's having a thickness of 3,000 layers is deposited on the entire surface of an insulating substrate 12 made of a glass plate by a sputtering method. A thick Ta metal film was deposited. By buttering this Ta metal film by photolithography and etching,
Gate bus wiring 2 and additional capacitance electrode 3 were formed.

Next, as shown in FIG. 2(a), a positive photoresist 1 is applied to the entire surface of the gate bus wiring 2 and the additional capacitance electrode 3.
3 was applied. Next, exposure is performed from the back side of the substrate 12,
A photoresist 13 was formed on the gate bus wiring 2 and the additional capacitance electrode 3 in a self-aligned manner (FIG. 2(b)).

Next, the gate bus wiring 2 and the additional capacitance electrode 3 were anodized, and Ta205 anodic oxide films 4a and 4b were formed on both sides of the gate bus wiring 2 and the additional capacitance electrode 3. Next, after removing the photoresist 13, the substrate 12
A gate insulator M5 made of SiN with a thickness of 3,000 yen was formed on the entire surface by plasma CVD. Furthermore,
A-3T(i) with a thickness of 300 on the entire surface of the substrate 12
A protective insulating film 7a (FIG. 1(a)) and a SsNx layer with a thickness of 3,000 yen are laminated in order, and this SfN layer is patterned by photolithography and etching. A protective film 7C (FIG. 1(b)) of No. 2 was formed. The protective insulating film 7a is provided to protect the portion that will become the semiconductor layer 6 after the a-5t(i) layer located therebelow from the etchant.

Next, an n+ type a-Si layer doped with P (phosphorus) to a thickness of a loCIQ person is formed by plasma CVD on the entire surface of the a-3i(f) layer, the protective insulating film 7a, and the second protective film 7c. deposited by the above a-3i(1) layer and n+ type a-
The SL layer is simultaneously patterned to form the semiconductor layer 6 (FIG. 1(a)), the first protective film 6c (FIG. 1(b)), and the contact layers 8a, sb (FIG. 1(a)) and A third protective film 8c (FIG. 1(b)) was formed.

Next, a T1 metal layer was deposited on the entire surface of the substrate 12 to a thickness of 3000 Å, and this Ti metal layer was patterned to form a source bus wiring 19, a source electrode 9a, and a drain electrode 9b.

Through the above steps, the TFT 20 is obtained. Further, a transparent conductive film made of ITO having a thickness of 500 nm was deposited and then patterned by photolithography and etching to form the picture element electrode 10. The picture element electrode 10 is electrically connected to the drain electrode 9b of the TFT 20. Further, the picture element electrode 10 also extends over the additional capacitor electrode 3, and the picture element electrode 10 and the additional capacitor electrode 3 constitute an additional capacitor R21. Only the gate electrode 5 is sandwiched between the picture element electrode 10 and the additional capacitance electrode 3. Further, as shown in FIG. 1(b), a transparent conductive film made of ITO was also left on the source bus wiring 19 in case the source bus wiring 19 was disconnected. Next, a protective film 11 was formed on the substrate 12.

A liquid crystal was sealed as a display medium between the active matrix substrate obtained as described above and a counter substrate (not shown) on which counter electrodes and the like were formed to obtain the active matrix display device of this example. Ta.

In this embodiment, the gate bus wiring 2 and the additional capacitance electrode 3 are
Since the anodic oxide films 4a and 4b are formed only on both sides of the gate bus line 2 and the additional capacitor electrode 3, the connection between the source bus line, the gate bus line, and the additional capacitor electrode 3 that occurs at the shoulder portions on both sides of the gate bus line 2 and the additional capacitor electrode 3 is reduced. This prevents poor insulation between the electrodes for additional capacitance and the picture element electrodes.

As shown in FIG. 1(b), the gate bus wiring at the intersection of the gate bus wiring 2 and the source bus wiring 19! ! !
2, a gate insulating film 5, a first protective film 6c, a second protective film 7c, and a third protective film 8C are formed. At the intersection between the additional capacitance electrode 3 and the source bus wiring 19, four layers of an anodic oxide film 4b, a gate insulating film 5, and protective films 6Cs7c and 8c similar to those shown in FIG. 1(b) are formed.

In this embodiment, unlike the conventional example described above, an anodic oxide film is not formed on the gate bus wiring 2 and the additional capacitance electrode 3, so that the gate bus wiring 2 and the additional capacitance electrode 3 are connected to the source bus wiring. The source bus wiring 19 is less likely to be disconnected at the intersection with the source bus wiring 19. Further, since the distance between the additional capacitor electrode 3 and the picture element electrode 10 can be set small, the width of the additional capacitor electrode 3 can be reduced. Therefore, a display screen with a large aperture ratio can be obtained.

According to the method for manufacturing an active matrix display device of this embodiment, the anodic oxide films 4a and 4b can be formed on both sides of the gate bus wiring 2 and the additional capacitance electrode 3 in a self-aligned manner. Further, according to the manufacturing method of this embodiment, the upper surfaces of the gate bus wiring 2 and the additional capacitance electrode 3 are not anodized. Therefore, the layer thickness of the gate bus wiring 2 and the additional capacitance electrode 3 can be increased, and compared to the gate bus wiring and the additional capacitance electrode produced in the conventional example,
Even though they have the same width, they can have low resistance.

In this embodiment, an example has been described in which a part of the gate bus wiring 2 functions as a gate electrode, but the present invention can also be applied to a case where the gate electrode is branched from the gate bus wiring. In this case, an anodic oxide film is also formed on both sides of the branched gate electrode.

(Effects of the Invention) In the active matrix display device of the present invention, by providing an anodic oxide film on both sides of the gate bus wiring and the additional capacitance electrode, the insulation between the gate bus wiring and the source bus wiring is improved. Defects and insulation defects between the additional capacitance electrode and the picture element electrode are reduced. Further, disconnection of the source bus wiring does not occur. Furthermore, the width of the additional capacitance electrode was made smaller (
Therefore, the aperture ratio of the display screen can be increased. Therefore, the active matrix display device of the present invention has high image quality and can be manufactured at a high manufacturing yield.

Further, in the method for manufacturing an active matrix display device of the present invention, since the anodic oxide film can be formed in a self-aligned manner, the above-mentioned active matrix display device can be manufactured in a relatively simple process. Furthermore, according to the manufacturing method of the present invention, the resistance of the gate bus wiring and the additional capacitance electrode can be reduced, so the width thereof can be reduced, and an active matrix display device with a large aperture ratio can be obtained. can.

4. Simple removal of B FIG. 1(a) is a sectional view of an active matrix substrate constituting an embodiment of the active matrix display device of the present invention, and FIG. 1(b) is a sectional view of the active matrix substrate of FIG. 1(a). Cross-sectional view of the intersection of gate bus wiring and source bus wiring on the substrate, 2nd
Figures (a) and (1)) are diagrams showing the photoresist forming process in the manufacturing process of the substrate in Figure 1 (a), and Figure 3 (a).
) is a sectional view of a conventional active matrix substrate, and FIG. 3(b) is a sectional view of the intersection of gate bus wiring and source bus wiring in the substrate of FIG. 3(a).

1...Base coat film, 2...Katehas wiring, 3
...Additional capacitance electrode, 4a, 4b...Anodic oxide film,
5... Gate insulating film, 6... Semiconductor layer, 7a...
Protective insulating film, 8 a, 8 b-=contact layer, 9
a... Source electrode, 9b... Drain electrode, 10.
...Picture element electrode, 11...Protective film, 12...Insulating substrate, 13...Photoresist, 19...Source bus wiring, 20...TFT, 21...Additional capacitance.

that's all

Claims (1)

[Claims] 1. An active matrix display device having a picture element electrode formed on an insulating substrate, a thin film transistor connected to the picture element electrode, and a gate bus wiring connected to the thin film transistor. An active matrix display device in which an anodic oxide film is formed on both sides of the gate bus wiring. 2. An active matrix display device having a picture element electrode formed on an insulating substrate and an additional capacitance electrode facing the picture element electrode, wherein an anodized film is provided on both sides of the additional capacitance electrode. active matrix display device. 3. Forming gate bus wiring on an insulating substrate; Applying photoresist to the entire surface of the substrate; Exposure from the back side of the substrate to form photoresist on the top surface of the gate bus wiring. 2. The method of manufacturing an active matrix display device according to claim 1, comprising the steps of: forming an anodic oxide film on both sides of the gate bus wiring. 4. A step of forming an electrode for additional capacitance on an insulating substrate, a step of applying a photoresist on the entire surface of the substrate, and a step of exposing the back side of the substrate to form a photoresist on the upper surface of the electrode for additional capacitance. 3. The method of manufacturing an active matrix display device according to claim 2, comprising the steps of: forming an anodic oxide film on both sides of the additional capacitance electrode.