JPH047592B2 - - Google Patents

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a composite thyristor in which a main thyristor and an auxiliary semiconductor element for triggering are formed on one semiconductor substrate. It is applied to thyristors that control with low power and obtain high dv/dt withstand capability.

(Prior technology) In large current thyristors, sufficient
In order to provide dv/dt tolerance, a short-circuited emitter structure is often used. In this case, the gate current is several tens of mA
As described above, it is not possible to easily downsize the control power source for the thyristor.

In this regard, it has been conventional practice to provide an auxiliary thyristor. FIG. 3 is a sectional view of a conventional example of a composite thyristor in which such a main thyristor and an auxiliary thyristor are arranged side by side on one semiconductor substrate. As shown in the figure, the main thyristor 8 has an N ⁺ emitter region 1 , a P base region 2 , an N ^- base region 3 , and a P emitter region 4 stacked on one semiconductor substrate 3 . N ⁺ emitter region 1 is divided into a plurality of emitters, a part of P base region 2 is exposed on the main surface of the substrate, and these are short-circuited to each other by cathode electrode 5 . As is well known, this shorted emitter structure increases the dv/dt capability of the main thyristor 8. The gate current for turning on the main thyristor 8 is generally several tens of milliamps or more, and the external control power supply connected to the gate electrode 6 must also have a large capacity, making it difficult to miniaturize it. In order to improve this problem, an auxiliary thyristor 9 is provided in parallel. The auxiliary thyristor 9 is as shown in Fig. 3.
This is a stack of an N ⁺ emitter region 1a, a P base region 2a, an N ^- base region 3a, and a P emitter region 4a. The cathode electrode 5a and the gate electrode 6 of the main thyristor are connected to each other by external wiring.

When a gate trigger signal is applied to the gate electrode 6a of the auxiliary thyristor to turn on the auxiliary thyristor, this on-current becomes the gate current of the main thyristor, and the main thyristor is turned on. Generally, the gate trigger current of the auxiliary thyristor is small, and this small current can turn on the composite thyristor. Therefore, the control power source for the composite thyristor can be of low power and can be easily miniaturized.

However, the auxiliary thyristor is structurally connected in parallel with the main thyristor. Therefore, the dv/dt capability of this composite thyristor is determined by the capability of the element with the weaker dv/dt capability of the two thyristors, that is, the auxiliary thyristor, and therefore has a low value.

(Problems to be Solved by the Invention) As mentioned above, the auxiliary thyristor that does not have a short-circuited emitter structure has a high gate sensitivity of several μA to several hundred μA, and the gate trigger current of the main thyristor is approximately several hundred mA. Since it is sufficient to have a cathode area that can be used, a small area can be added to the main thyristor. This facilitates switching of the thyristor and solves the problem of miniaturization of the control power supply.

However, since the auxiliary thyristor does not have a shorted emitter structure, its dv/dt tolerance is lower than that of the main thyristor. In other words, when a high voltage is applied to this composite thyristor in the off state, displacement current flows through each of the two thyristors, but the displacement current flowing through the auxiliary thyristor is amplified by the transistor action of the N ⁺ PN ^- layer. Therefore, it becomes easier to turn on at low dv/dt values, reducing the dv/dt withstand capability of the composite thyristor. In other words, the main circuit is limited by the dv/dt tolerance of the auxiliary thyristor, making it impossible to provide versatility.

The purpose of the present invention is to improve the problem of conventional composite thyristors that switching can be performed with small power but low dv/dt withstand capability, and to provide a composite thyristor that has high gate sensitivity and high dv/dt withstand capability. It is to be.

[Structure of the Invention] (Means and Effects for Solving Problems) The composite thyristor of the present invention includes a bipolar insulated gate field effect transistor (Insulated Gate Field Effect Transistor) in place of a main thyristor and a conventional auxiliary thyristor.
Bipolar Transistors (IGBTs) are arranged side by side on a single semiconductor substrate. The structure of IGBT is similar to that of conventional insulated gate vertical field effect transistor (VD
MOS FET (MOS FET or V MOS FET)) is an additional layer with an opposite conductivity type region in contact with the drain region of one conductivity type, and combines the high speed and high input impedance characteristics of a MOS FET with the high conductivity characteristics of a bipolar transistor. It is a new element.
The gate electrode of the main thyristor and the source electrode of the IGBT are connected by electrode wiring, and the on-state current of the IGBT becomes the gate current of the main thyristor. Also IGBT dv/
The dt tolerance is large and the on-current is sufficiently large.

Therefore, the composite thyristor of the present invention in which a main thyristor and an IGBT are arranged in parallel can turn on the main thyristor with extremely small control power and provide high dv/dt withstand capability, thereby solving the above-mentioned problems.

(Example) Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a composite thyristor of the present invention, in which a main thyristor 20 is mounted on one semiconductor substrate 10.
and a bipolar MOS FET (IGBT) 30 are installed in parallel.

The main thyristor 20 extends from the first main surface of the substrate 10 to the second main surface on the opposite side, parallel to the main surface.
An N ⁺ emitter region 21, a P base region 22, an N ^- base region 23, and a P emitter region 24 are stacked. The N ⁺ emitter region 21 is divided into a plurality of parts and is short-circuited with a portion of the P base region 22 exposed on the substrate surface by the cathode electrode 25, forming a so-called short-circuited emitter structure.

The IGBT 30 is a double-diffused insulated gate vertical field effect transistor (VD MOS FET) in which a P-type region (hereinafter referred to as a P-drain region) 34 is additionally laminated in contact with an N ^- drain region 33. This VD MOS FET has an N ⁺ source region 31 formed in the surface layer of the first main surface of the substrate, a channel forming portion 32a of a P body region (also called a base region) 32, and an N ⁻ source region in contact with the P body region 32. drain region 33, gate oxide film 35,
It is composed of a gate polycrystalline silicon film 36 and the like.

In this embodiment, the N ^- drain region 33 of the IGBT is an extended region of the N ^- base region 23 of the main thyristor, and the P drain region 33 of the IGBT is an extended region of the N - base region 23 of the main thyristor.
is the extended region of the P emitter region 24 of the main thyristor. Further, the P base region (gate layer portion) 22 of the main thyristor 20 and the N ⁺ source region 31 of the IGBT 30 are electrically connected to each other by a low resistance wiring electrode film 26 to form a composite thyristor. Note 2
7 is a main electrode film (anode electrode) common to the main thyristor and IGBT, 25 is a cathode electrode, and 37 is a common main electrode film (anode electrode) of the main thyristor and IGBT.
Gate electrode of IGBT, 28 is thermal oxide film, 29 is
It is a CVD insulation film.

Next, the operation of this composite thyristor will be explained. The main thyristor is a known one, and has a short-circuited emitter structure to increase dv/dt withstand capability. The outline of the operation of the IGBT 30 is as follows.
When a positive electrode is applied to the gate electrode 37, the channel forming portion 32a under the gate electrode becomes an inversion layer.
Forms N channels. A large number of carriers (electrons) flow from the N ⁺ source region 31 to the N ^- drain region 33 via the inversion layer 32a, and the IGBT is turned on. This point is similar to VD MOS FET, but
In IGBT, when a large number of carriers flow into the N ^- drain region 33, the N ^- drain region 33 and P
The PN junction with the drain region 34 becomes more forward biased, and minority carriers (holes) are injected from the P drain region to the N ^- drain region. That is, electrons are injected from the source region and holes are injected from the P drain region into the N ^- drain region 33, and these excessively injected carriers cause N ^-
The resistance of the drain region 33 is significantly reduced. This eliminates the presence of a large resistance component in the drain region, which was a major obstacle when attempting to increase the voltage resistance of conventional VD MOS FETs. That is,
IGBTs have a high breakdown voltage, can switch large currents with a small amount of gate power, and have a small on-state voltage.
It is a new element with high dv/dt tolerance. In addition
The turn-off operation of the IGBT is performed by lowering the voltage applied to the gate electrode below the threshold voltage, similar to the VD MOS FET.

In this composite thyristor, the gate current of the main thyristor 20 is approximately equal to the on-state current of the IGBT 30, so the current of the main thyristor is
Can be controlled with a small gate power of dv/dt
The withstand capacity is also increased and the problems of the conventional method can be solved. In addition, in this composite thyristor, if the main thyristor is a normal piborar type, the single thyristor structure and the chip area of the IGBT section are sufficient even for large current applications, and the IGBT section can also obtain a current of about several hundred mA. It only takes up a small area. In addition, the N ^- base region of the main thyristor can be deepened by 30 μm or more, and when placed outside, it is easy to obtain a withstand voltage of about 600V.

Next, an outline of the method for manufacturing a composite thyristor of the present invention will be explained. FIGS. 2a to 2h are cross-sectional views showing this manufacturing process. As shown in figure a, first N ^-
A substrate 10 is prepared, and oxide films 28a are formed on both main surfaces of the substrate.
and pattern it to a predetermined size. Next, as shown in Figure b, a P ⁺ diffusion layer 40 for element isolation is made, and
A P drain region 34 of the IGBT is formed. Next, as shown in figure c, the P base region 2 of the main thyristor
2 (including the gate layer portion) and the P body region 32 of the IGBT are separated from each other and diffused into the N ⁻ base region 23 and the N ⁻ drain region 33, respectively. Next, as shown in FIG. 4D, impurities are selectively diffused into the P base layer 22 to form N ⁺ emitter regions 21 divided into a plurality of parts. Next, as shown in figure e, the oxide film 28a is removed, and a new thermal oxide film 28,
Gate insulating film 35 and gate polycrystalline silicon film 3
6 to form the IGBT MOS gate part.

Using this as a mask, a P ⁺ body region 32b is formed by diffusion. Next, as shown in FIG. 5F, the N ⁺ source region 31 is formed by diffusion using the same mask, and the channel length of the channel forming portion 32a is determined. Next, as shown in FIG.
After forming the (CVD film), the cathode electrode 25 of the main thyristor, the wiring electrode film 26 and the gate electrode 3 of the IGBT
form 7. Next, as shown in FIG. 1H, a main electrode 27 serving both as the anode electrode of the main thyristor and the drain electrode of the IGBT is formed to obtain the composite thyristor shown in FIG.

In this embodiment, a composite thyristor of a preferred embodiment has been described, but the present invention is a composite thyristor in which a main thyristor and an IGBT are arranged side by side on one semiconductor substrate. 1 with semiconductor substrates pasted together
It is also possible to use two composite semiconductor substrates,
The mode of juxtaposition is also not limited to this example. Furthermore, the present invention can be applied even if the conductivity type of the semiconductor is changed between N type and P type.

[Effects of the Invention] High dv/dt withstand capability and high sensitivity of the thyristor are requirements necessary for miniaturization of the control power supply and simplification of the main circuit. One method is to create a composite thyristor in which a highly sensitive auxiliary thyristor is connected in parallel with the main thyristor, but in this case, the dv/dt
Since the withstand capacity is dominated by the withstand capacity of the auxiliary thyristor, it is necessary to increase the dv/dt capacity of the auxiliary thyristor.

Focusing on this point, the composite thyristor of the present invention is a new bipolar type that maintains high dv/dt tolerance when the gate is off, and can easily flow the trigger current of the main thyristor with a small gate power.
This is a MOSFET formed in place of an auxiliary thyristor. Therefore, the composite thyristor of the present invention has high gate sensitivity and high dv/dt tolerance. This allows easy control using an IC that can provide an output voltage of, for example, several volts.
Also, the chip size requires only a small area as mentioned above.
It becomes possible to downsize and simplify the circuit.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a composite thyristor of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the composite thyristor of the present invention, and FIG. 3 is a cross-sectional view of a conventional composite thyristor. 10... Semiconductor substrate, 20... Main thyristor,
21... Emitter region of one conductivity type (N ⁺ emitter region), 22... Base region of opposite conductivity type (P base region), 23... Base region of one conductivity type (N ^- base region), 24... Opposite conductivity type Emitter region (P emitter region), 30...Bipolar type insulated gate field effect transistor (bipolar type MOS
FET or IGBT), 31... one conductivity type source region (N ⁺ source region), 32... opposite conductivity type body region (P body region), 32a... channel forming part,
33... Drain region of one conductivity type (N ^- drain region), 34... Region of opposite conductivity type to be additionally laminated (P
drain area).

Claims (1)

[Claims] 1. In one semiconductor substrate, (a) an emitter region of one conductivity type and a base region of the opposite conductivity type extending from the first principal surface of the substrate to the second principal surface on the opposite side, parallel to the principal surface; , a main thyristor comprising a base region of one conductivity type and an emitter region of the opposite conductivity type laminated in this order; (b) a source region of one conductivity type and a body region of the opposite conductivity type on the surface layer of the first main surface of the substrate; An insulated gate vertical field effect transistor comprising a channel forming portion and a drain region of one conductivity type in contact with the body region; A composite thyristor characterized by having a gate field effect transistor and a gate field effect transistor arranged in parallel. 2. The drain region is a region extending from a base region of one conductivity type of the main thyristor, and the additional stacked region of the opposite conductivity type is a region extending from an emitter region of the opposite conductivity type of the main thyristor. Compound thyristor as described in section.