JPH047629B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention uses raster scanning to scan a light spot.
The present invention relates to a pattern drawing device that draws a two-dimensional pattern by scanning dimensionally. 2. Description of the Related Art Conventionally, as a drawing apparatus of this type, there is an apparatus which draws a precise pattern on an artwork film for a printed circuit board or the like by scanning and modulating a laser beam. This device has the advantage of being able to draw patterns in a few minutes, which would require several hours with a photoplotter, but it has the following disadvantages. The base of artwork film for printed circuit boards is made of polymeric materials such as polyester, and because of this, it expands and contracts significantly due to the effects of humidity and temperature. The degree of expansion and contraction is for a 1% change in relative humidity.
A 500mm length will expand by 8mm, and a 500mm length will expand by 8mm even with a temperature change of 1°C. Although it is relatively easy to control changes in room temperature to within ±1°C, controlling humidity is difficult, and extremely expensive air conditioning equipment is required to keep relative humidity changes within ±10%. . For this reason, even after the drawing film is drawn and a circuit pattern is formed, it expands and contracts, and depending on the environment when used as a mask, one had to be prepared for a change of about 0.1 mm per 500 mm. On the other hand, the wiring width on printed circuit boards has become narrower year by year, and widths of 0.11 to 0.14 mm have come to be used in multilayer circuit boards. The alignment between layers in such a multilayer substrate must be performed with an error of about 0.05 or less. However, as mentioned above, the film that serves as a mask for the circuit pattern expands and contracts by about 0.1 mm, so it is not possible to use only artwork film drawn with a certain scaling (a certain amount of enlargement and reduction) for a 500 mm x 600 mm It was not possible to obtain the necessary positioning accuracy for the entire surface of a circuit board of this size. For this reason, it has been common practice to create a plurality of artwork films in advance with drawings with slightly different scaling, and to use the artwork film with the most suitable scaling when printing onto a printed circuit board. In a pattern drawing device that uses a photo plotter, it is easy to make minute changes in scaling as described above, but in a device that draws by raster scanning a laser spot, the drawback is that the pattern cannot be expanded or contracted continuously. It was hot. The reason for this is that the drawing pattern is composed of pixels of a fixed size. for example,
Pixel size is 25μm (0.025mm) x 25μm (0.025mm)
Made of 500mm long pattern with 0.05mm
If you want to reduce the size, one possible method is to thin out two pixels out of 500mm. However, with this method, the line width etc. of the wiring may vary depending on the location.
A new drawback arises: a difference of 0.025 mm. The present invention solves these drawbacks and provides a pattern drawing device that can obtain good line width accuracy even with minute scaling changes. A pattern drawing apparatus according to the present invention is an apparatus that draws a pattern on an object by irradiating or not irradiating each pixel with a drawing beam based on drawing data when one scanning line of a drawing beam is converted into pixels. Within one scanning period, a drawing pulse train with a number of pulses corresponding to the number of pixels in a scanning line is generated, and in the drawing pulse train, the periods of at least two discrete pulses are set relative to the periods of other pulses. The present invention is characterized in that it includes a drawing pulse generating device that expands and contracts, and by writing with the period of each pulse of the drawing pulse train as one pixel, the pattern width in the scanning line direction is expanded and contracted. Embodiments of the present invention will be described below based on the drawings. FIG. 1 is a perspective view of a pattern drawing apparatus according to an embodiment of the present invention. The laser beam emitted from the laser light source 1 is intensity-modulated by the optical modulator 2, and the width of the beam is expanded by the beam expander 3, after which the laser beam is sent to the rotating polygon mirror 4 in the counterclockwise direction, that is, in the direction of the arrow 5. The light is reflected and deflected by the rotation of the light beam, focused by the fθ lens 6, and incident on a predetermined position of the reflecting mirror 7. The reflecting mirror 7 functions to convert the horizontally incident beam downward. The downward beam, that is, the laser spot, forms an image on the photosensitive material 9 on the one-dimensional moving stage 8, and is linearly scanned in the output direction (x direction) of the arrow 10 while blinking due to the action of the optical modulator 2. Ru. This photosensitive material 9 is made of a photosensitive material such as a silver halide film or a diazo film, and is fixed on the stage 8 by vacuum suction or the like. Further, the stage 8 is placed on the pedestal 11, and is moved by an arrow 10 on the pedestal 11 using a screw 12 and a motor 13.
move in the perpendicular direction (y direction). Therefore, as mentioned above, the laser spot is scanned in the direction of arrow 10 (x direction), and the stage 8 is scanned in the direction of arrow 10 (x direction).
Since it moves in the direction perpendicular to (y direction), a two-dimensional pattern is drawn on the photosensitive material 9. Note that the rotation speed of the rotating polygon mirror 4 is as follows:
It is controlled by a rotating polygon mirror control section 14. Further, the optical modulator 2 is controlled by a data modulation section 15. This data modulation section 15 is supplied with the output of a laser scanning synchronization detector 16 . The laser scanning synchronization detector 16 is provided at the starting point of the scanning trajectory of the laser beam on the reflecting mirror 7, and detects the timing of synchronizing the starting points of each raster of laser spot scanning. Furthermore, the data modulation section 15 includes:
Drawing data 17 is supplied from outside the drawing device,
It has a function of correcting the drawing magnification and synchronizing the drawing timing in the process of outputting data to the optical modulator 2, and corresponds to the drawing pulse generator of the present invention. A motor 13 that controls the movement of the one-dimensional moving stage 8 is controlled by a stage control unit 18, and is controlled to move at a predetermined speed during drawing, and at a high speed when not drawing. These rotating polygon mirror control section 14, data modulation section 15, and stage control section 18
are all controlled by the central control section 19. Next, details of the data modulation section 15 will be explained based on the drawings. FIG. 2 is a block circuit diagram of the data modulation section 15. The output of the laser scanning synchronization detector 16 passes through the preamplifier 21 and becomes a digital signal 38a with a logic value of "1" or "0" by the comparator 22.
When the signal 38a is "1", the timer (hereinafter TM
signal delayed by a minute time Tm by 23 (abbreviated as )
Becomes CL. The delay time Tm due to this TM23 is
This is to provide a time corresponding to the time difference between when the laser spot is incident on the laser scanning synchronization detector 16 and when drawing actually starts. This delayed signal CL is supplied to the OR circuit 24, and
The signal is supplied to a quinary counter (hereinafter abbreviated as CC) 39 and a counter (hereinafter abbreviated as CB) 36 which will be described later.
The counter (hereinafter abbreviated as CA) 25 has an OR circuit 2
A preset command PR from 4 is supplied, and preset data is supplied from a latch circuit (hereinafter abbreviated as LT) 26. The CA 25 counts down the clock signal CK from the oscillator 27 from the data preset by the LT 26, and outputs a zero signal 28 when the count value reaches zero. Zero signal 28
is supplied to the OR circuit 24, so CA2
5 is a period corresponding to a preset count value, and a zero signal 28 is output at fixed time intervals, the phase of which is synchronized with the detection signal of the laser scanning synchronization detector 16. On the other hand, reset data 29 is supplied to the LT 26 from outside the drawing device. Further, from outside the drawing device, a code signal 30 for expanding and contracting the pattern is sent to an inverter 31 and an AND circuit 32.
is supplied to The output signal of the inverter 31 and the zero signal 28 are supplied to an AND circuit 33, and the output signal thereof is supplied to an OR circuit 34. AND circuit 3
2 is supplied with a zero signal 28 in addition to the code signal 30,
The output signal is supplied to an OR circuit 35. In addition to the above-mentioned inputs, the OR circuit 34 and the OR circuit 35 are also supplied with the output of a compensation circuit consisting of a CB 36 and a ROM 37. The CB 36 and the ROM 37 are compensation circuits having a function of changing the scaling value depending on the position of the laser spot scan. The reason for providing such a function is that it is necessary to correct deviations from the fθ characteristics of the fθ lens 6, but if you try to improve the performance of the fθ lens 6, the manufacturing cost will increase, so it is necessary to correct the deviation below a certain value. This is because it is done electrically. CB36 is a counter that counts the length from the drawing start point to the drawing end point in one-dimensional spot scanning. The oscillator 27 outputs the clock signal CK based on the output signal 38a of the comparator 22, and outputs the clock signal CK from the output signal 38a of the comparator 22.
6 counts the clock signal CK in response to the output signal CL of the TM 23, and returns to zero when it counts, for example, 10,000, which corresponds to the number of pixels in a certain scanning line to be drawn. 2
7 and stops the output of the clock signal CK. In addition, the count output signal of the CB36 is written by measuring the amount of correction of the fθ lens 6 in advance.
It is supplied to the ROM 37 as an address signal. This ROM 37 has written information instructing whether to delay or advance the clock signal CK by 1/5 cycle when the one-dimensional spot scan reaches a certain position. Here, it is assumed that the scanning position at which the clock signal CK by the ROM 37 is switched is determined so as not to overlap the scanning position at which the output of the CA 25 changes, that is, the scanning position at which the zero signal 28 is output. For example, the preset data 29 to the LT 26 may be a multiple of 100, and the position at which the ROM 37 can cut may be determined from the drawing start position to the clock signal CK so that it is not a multiple of 100. Now, the outputs of the OR circuit 34 and the OR circuit 35 are supplied to the CC 39 as an up input and a down input, respectively. The count output signal of CC39 is supplied to the decoder 40, and the decoder 40
5 signal lines 4 according to the count output of CC39
It has a function to select and output any one of 0A to 40E. Therefore, the truth values of the input and output of the decoder 40 have the relationship shown in the following table.

[Table] Output signals 40A to 40E of the above decoder 40
is a clock delay circuit (hereinafter abbreviated as CKDL) 4
1. This CKDL41 is the decoder 4
The signals 40A to 40E from oscillator 27
It has a function to periodically delay or advance the phase of the clock signal CK from the output signal 4.
2 is supplied to a parallel-serial converter (hereinafter abbreviated as PS) 43 as a drawing pulse signal. this
The drawing data 17a is temporarily stored in the PS 43 in accordance with an external timing signal 17b.
The drawing data 17a is, for example, an 8-bit parallel signal, but the PS 43 is a drawing pulse signal 42.
Since the drawing data 17a is output as a serial signal periodically with the clock, the output signal 44 to the optical modulator 2 becomes a serial signal. Next, details of the CKDL 41 of the data modulation section will be explained based on the drawings. FIG. 3 is a block circuit diagram of CKDL41. Delay circuit 50A, 50B, 50C, 50D
are connected in series, and the delay time of each delay circuit is determined by the clock signal from the oscillator 27.
It is set to be 1/5 of the CK cycle. AND circuits 51A, 51B, 51C, 51D, 51
Output signals 40A, 40B, 40C, 40D, and 40E from the decoder 40 are supplied to one input of E, and these signals are either the clock signal CK or the clock signal delayed by the delay circuit. Only one of the signals has a logic value of "1" and the others have a logic value of "0" so that one of the signals is selected (see Table 1). Each output signal 51A, 52B, 52C, 52D, 5 of AND circuit 51A, 51B, 51C, 51D, 51E
2E is supplied to a 5-input OR circuit 53 and output as a drawing pulse signal 42 with a controlled delay time. Next, details of the PS 43 will be explained based on the drawings. FIG. 4 is a block diagram of PS43. A drawing pulse signal 42 from the CKDL 41 is supplied to a shift register (hereinafter abbreviated as SR) 54 and a counter (hereinafter abbreviated as CNT) 55. This SR
Reference numeral 54 denotes a circuit for inputting 8-bit parallel data 17a of drawing data from a drawing data generator (not shown) and serially outputting it. CNT55
is an octal counter which counts the output signal 42 by 8 and outputs a request signal 17c to a drawing data generator (not shown) each time the count value becomes zero. Note that this drawing data generation device (minicomputer, microcomputer, etc. processing device, magnetic recording, etc.)
The drawing data 17a, timing signal 17b, and the aforementioned data 29 and code signal 30 are supplied from the optical recording device. Next, the operation of each part of the drawing pulse generator of this embodiment having the above-described configuration will be explained based on a time chart. FIG. 5 is a time chart showing the operation of each part in FIG. 2. In synchronization with the rise of the output signal 38a of the comparator 22, which is output in conjunction with the operation of the laser scanning synchronization detector 16, the oscillator 27 starts outputting the clock signal CK. The phase of the oscillation is synchronized with the rising timing of the signal 38a.
The output signal 38b of the CB 36 is output when the drawing time for one raster ends, and the oscillator 27 stops outputting the clock signal CK in accordance with this rising edge. In other words, CB36 is the output signal of TM23
Clock signal CK in response to CL (delay time Tm)
starts counting, and when the count corresponds to the drawing time of one raster, for example 10000, it returns to 0 (0 → 9999 → 0), and when it returns to 0, the clock signal of the oscillator 27 is activated by the signal 38b.
This is to stop the output of CK. In this way, a number of clocks equal to the number of pixels required to draw one scanning line is obtained within time _t1 . Now, in actual pattern drawing, the operation when the drawing pattern is lengthened by 0.01% in the scanning direction will be explained. Note that one scanning line has 10,000 pixels.
In this case, the length of the laser spot drawn by 10,001 scanning lines can be determined by using the clock signal CK of the oscillator 27, and the drawing pattern can be drawn by using 10,000 pulses (10,000 pixels) of the drawing pulse signal 44. In other words, the clock signal CK is controlled by CKDL41.
It is sufficient to generate a drawing pulse signal 42 in which the period of one clock is lengthened by 1/5 period at five discrete points among the 10,000 clocks. Therefore, first, data 29
, input 10000/5=2000 to LT26. Further, as the code signal 30, since the pattern is made long, a logic value "0" is given. FIG. 6 is a time chart showing the relationship between the count of CA 25 and the zero signal 28 in FIG. CA25 is preset to 2000 as preset data via LT26. This preset is set at the output of the OR circuit 24, that is, at the rising edge of the preset command PR. Therefore, at the start of one scanning line, data 2000 is set to CA25 at the rising edge of the delayed pulse signal CL, and CA25 is set in the middle.
It is set at the rising edge of the zero signal 28 which is the output of . Also, one pulse of the zero signal 28 is a clock signal.
Synchronized with one pulse of CK, CA25 is a clock signal
Countdown at the rising edge of CK. In other words,
At the rising edge of the clock signal CK, CA25 becomes 0, so the zero signal 28 becomes ``1'', and as a result, preset data 2000 is set at the rising edge of the clock signal CK. Normally, the zero signal 28 would become "0" immediately after the preset data is set, but since it is synchronized with the clock signal CK, the clock signal
It becomes "0" together with CK. Now, when the CA 25 starts counting the clock signal CK in response to the signal CL, only the AND circuit 33 of the AND circuits 32 and 33 closes its gate because the sign signal 30 has a logical value of "0". Since it is open, the count output value of CC39 is "0"
It is. Therefore, the DEC 40 sets only the signal 40A to the logical value "1", the CKDL 41 opens the gate of the AND circuit 51A shown in FIG.
occurs as. Now, when the CA 25 outputs the zero signal 28, that signal is applied as an up input to the CC 39 via the AND circuit 33 and the OR circuit 34, and the count value of the CC 39 becomes "1". At this time, from Table 1 above, the DEC40 has a signal of 40B.
Since only the logical value is set to "1", CKDL41 is
A signal 52B delayed by 1/5 period from the clock signal CK by the delay circuit 50A is generated from the OR circuit 53 as the drawing pulse signal 42. That is, when the zero signal 28 is output, the drawing pulse signal 42 is the clock signal CK, which is the signal 5.
2A is switched to a signal 52B delayed by 1/5 period with respect to the clock signal CK. FIG. 7 is a time chart showing the operation. Signals 52A to 52E have periods TP and 52E, respectively.
These are clock signals with a duty of 50%, and these signals are shifted by a time θ, that is, TP/5.
Since the CKDL41 selects and extracts one of these signals, the output of the decoder 40 is connected to the terminal 40.
When switching from A to 40B at the point of broken line 70, the length of one pulse T ₇₁ becomes longer by TP/5, as shown by signal 42a in FIG. It continues regularly with the phase delayed by θ with respect to 52A. Time TP (1 cycle) is 1
However, when switching as described above, the pulse period t ₂ at that time becomes longer than the above TP, the scanning distance for that one pixel becomes longer, and the drawing pattern will grow. Now, CA25 outputs one zero signal 28 every time 2000 clock signals CK are supplied, and CC3
Since the count output value of 9 outputs the zero signal 28 five times while the clock signal CK is supplied 10,000 times, the count increases sequentially, and the output of the decoder 40 also increases to 40A in response to the generation of the zero signal 28. →4
It changes as 0B → 40C → 40D → 40E → 40A. Therefore, the drawing pulse signal 42 from the CKDL 41 is the signal 52A→52B→52C in FIG.
→52D→52E→52A.
Of course, one pulse at each switching timing is longer than the period TP of other pulses by 1/5 period. FIG. 8 is a time chart showing the operation of the PS 43 in FIG. 4. After a 1-byte (8-bit) parallel input data signal 17a is supplied, an external clock 17b is supplied, and this clock 17b
is preset to SR54 by
4 is output as a serial signal in synchronization with the pulse of the drawing pulse signal 42 of the CKDL 41. When eight drawing pulse signals 42 are output from the CKDL 41, the data request signal 17c is output from the octal counter (CNT) 55, and at this timing, the next 1 byte of data appears in the input data signal 17a, and the signal level increases. Once valid, external clock 17b is applied and the next input data is converted from parallel to serial. To explain in more detail, the drawing pulse signal 42
A pulse of the request signal 17c appears at the 0th input of the drawing pulse signal 42, and a pulse of the external clock 17b is applied to the SR54 before the input of the 1st pulse of the drawing pulse signal 42 appears. At this time, the 8-bit data of the input data signal 17a is "99" in hexadecimal notation and "10011001" in binary notation.
If so, this data is converted into drawing pulse signal 4
The output signal 44 is serially output from the first pulse of 2, and the output signal 44 becomes a pulse train as shown in the figure. In this pulse train, pixels of "1" are drawn by the modulator 2, and pixels of "0" are not drawn.
The length of the logical value "1" or "0" of each pulse of this output signal 44 is determined by the drawing pulse signal 42.
corresponds to the period of the pulse train, so the period corresponding to five discrete pulses during one scan is different from the other periods,
(for pulses) becomes longer. For example, if the period of the first pulse of the drawing pulse signal 42 becomes longer by 1/5 period when the zero signal 28 is output for the first time after the clock signal CK is generated, then after the data 17a is updated, The period of the first pulse of the output signal 44 becomes longer by 1/5 period. In this way, out of the output signal 44 consisting of the number of pulses corresponding to the number of pixels in one scanning line (10000),
Discrete (every 2000 pulses) 5 pulse period is 1/5
The cycle becomes longer. As a result, the pattern is drawn as one scanning line that is one pixel longer than the one that is not scaled, and the pattern is drawn by 0.01% in the scanning direction.
A pattern enlarged by Now, when reducing the pattern, by setting the code signal 30 to the logical value "1", the zero signal 28 in FIG. 2 is supplied as a down input to CC 39 via the AND circuit 32 and the OR circuit 35. The output signal of the decoder 40 changes from 40A→40E→
It changes as 40D → 40C → 40B → 40A. Now, the output of the decoder 40 is 40A to 40A.
When switching to E, the pulse interval becomes T ₇₂ by one and becomes TP/5, as shown in signal 42b in Fig. 7.
However, the subsequent pulse train is signal 52.
It continues regularly with the phase leading by θ with respect to A. The pulse period t ₃ at this time becomes shorter than the above TP, the scanning distance for one pixel becomes shorter, and the drawing pattern is reduced. In this case as well, switching is performed at regular intervals, and CKDL
The drawing pulse signal 42 from 41 is 52A → 52E
→52D→52C→52B→52A. In this way, the CC 39 is switched to up-counting or down-counting depending on the sign signal 30 (logical value "0", "1"), and the zero signal 2
If 8 is given as an up input, the drawing pattern will be extended, and if it is given as a down input, it will be shrunk. The above explanation is about controlling the uniform drawing scale, but in this example, the fθ lens 6
It also has a function to correct errors, which will be explained below. FIG. 9 is a graph for explaining error correction of the fθ lens 6, and FIG. 9a shows the relationship between time t and laser spot scanning length x. The straight line 91 is the characteristic of an ideal fθ lens, and the curve 9
2 is the characteristic of an actual fθ lens with errors.
FIG. 9b shows the error △ of the curve 92 with respect to the straight line 91.
x ₁ is shown as a curve 93, and the error width is δ ₁ . In Fig. 9c, the error corresponding to △x ₁ is shown as a speed change as a curve 94, and in the same figure, based on the reference values 95 and 96, from time t ₀ to t ₁ the phase of the drawing clock is is advanced, the phase is delayed from time t ₂ to t ₃ , and time
If the phase is advanced from t ₄ , the position error △x ₂ of the drawn pattern will have the characteristic 97 as shown in Figure 9d.
, and the error is a value δ ₂ smaller than δ ₁ . Here, the times t ₀ , t ₁ , ... t ₄ do not indicate the clock switching times themselves; for example, between times t ₀ and t ₁ , the drawing clock is switched at regular intervals. ing. Furthermore, in FIG. 9c, a case has been described in which Δν is set in three steps, but correction is generally performed in even more steps. This kind of relationship between time and correction amount is stored in ROM37.
The stored information is stored in advance in the OR circuit 34 based on the output of the CB 36, that is, the scanning position information.
and 35, and similarly to the case of the zero signal 28 from CA 25, it supplies up and down inputs to CC 39. Each operation after CC39 is as described above. The above explanation is about scaling in the main scanning direction of raster scanning, but scaling in the direction perpendicular to this is due to the stage scanning speed,
That is, this is done by increasing or decreasing the moving speed of the motor 13. Further, in the above embodiment, the amount by which the clock signal is delayed by CKDL41 is set to 1/1/1 of the clock period.
Although the delay time is set to 5, it is also possible to divide the delay time into smaller parts of 1/6 or less. Furthermore, the duty of the clock signal CK of the oscillator 27 can be set to 25% or less, and the delay time can be increased to 1/2 of the period. In this case, two pixels expand or contract. Furthermore, if 1000 is input as preset data to the LT26 in the above example, the length of one pixel will be reduced to 1/5 for every 1000 pixels from the start of scanning one scanning line.
The pattern is expanded or contracted by the period, and the pattern is expanded or contracted by 10 discrete pixels in one scanning line. At this time, the expansion and contraction of the pattern is 0.02%. In this case, in FIG. 2, the CB36 counts the clock signal CK of the OSC27, but after counting the signal 42 of the CKDL41 to 10,000, the CB36 counts the clock signal CK of the OSC27.
b. As described above, according to the present invention, there is an advantage that even if the scaling of the drawn pattern is changed, the line width and positional accuracy of the drawn pattern are not deteriorated.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a pattern drawing device according to an embodiment of the present invention, FIG. 2 is a block circuit diagram of data modulation of the device, FIG. 3 is a block circuit diagram of CKDL of FIG. 2, and FIG. 4 is a block circuit diagram of the PS in Figure 2, Figures 5 and 6 are flowcharts showing the operation of each part in Figure 2, and Figure 7 is a flowchart showing the operation of the CKDL in Figure 3. Figure 8 is a flowchart showing the operation of the PS in Figure 4.
FIG. 9 is a graph for explaining error correction of the fθ lens. Drawing pulse generator; 15...data modulation section. Clock pulse generating means; 27... oscillator. Pulse phase shifting means; 25...Counter (CA), 26...Latch circuit (LT), 31...Inverter, 32, 33...AND circuit, 34, 35...OR circuit, 39...Counter (CC), 40...Decoder. Switching means; 41...Clock delay circuit (CKDL).

Claims (1)

[Scope of Claims] 1. In an apparatus for drawing a pattern on an object by irradiating or non-irradiating each pixel of one scanning line of a drawing beam with a drawing beam based on drawing data, the apparatus comprises: Within a period, a pulse train is input with the number of pulses corresponding to the number of pixels in the scanning line and each pulse has the same period, and in the pulse train, at least two discrete pulses are input.
The pattern width in the scanning line direction is provided with a drawing pulse generator that generates a drawing pulse train in which the period of one pulse is expanded or contracted with respect to the period of another pulse, and by drawing pixels of one scanning line according to the drawing pulse train, the pattern width in the scanning line direction is A pattern drawing device characterized by expanding and contracting. 2. The drawing pulse generation device includes clock pulse generation means for generating a clock pulse train whose pulse periods are all the same and whose number of pulses is equal to the number of pixels in one scan;
pulse phase shifting means for inputting the clock pulse train and generating N pulse trains sequentially shifted in phase by 1/N period; One pulse train is discretely N
2. The pattern drawing apparatus according to claim 1, further comprising a switching means for obtaining a drawing pulse train by switching output twice.