JPH0476526B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a compact distributed constant type electromagnetic delay line that handles ultra-high-speed signals with a rise time of 1 ns or less. Concerning good electromagnetic delay lines.

[Conventional technology]

Conventionally, as a distributed constant type electromagnetic delay line, as shown in FIGS. 7 and 8, a dielectric layer 3 is formed around the outer periphery of an elongated ground electrode 1.
It has been proposed that an inductance element 7 is constructed by forming a conductive line 5 in the shape of a single layer solenoid around the outer periphery of the inductance element 7.

Such an electromagnetic delay line is suitable for handling ultrahigh-speed signals, and has a distance T between the centers of conductive lines 5 facing each other in the thickness direction of the dielectric layer 3 (the same applies hereinafter) and a ratio T/P of the pitch P of the conductive lines 5. In particular, if T/P is selected in the range of 0<T/P<1, good delay characteristics can be obtained.

However, in such an electromagnetic delay line, it is generally considered that in order to increase the delay time per unit volume and to achieve further miniaturization, it is sufficient to reduce the pitch P and increase the density. In that case, if the size of the pitch P is reduced, there is a risk that good characteristics may not be obtained unless the distance T is also made smaller, based on the relationship between the pitch P and the distance T described above.

Regarding the width W of the conducting line 5, the smaller the width W, the more the inductance per unit length of the conducting line 5 increases, but the smaller the width W, the more the ground electrode per unit length of the conducting line 5. The capacitance between and decreases.

Therefore, the width W of the conductive line 5 has been selected mainly to set the characteristic impedance Zo of the inductance element 7 to a predetermined value. Note that the characteristic impedance Zo is determined from the inductance L and capacitance C per unit length of the conductive line 5 as Zo=√.

Therefore, in order to increase the delay time, there was no choice but to reduce the pitch P of the conducting lines 5, but as mentioned above, it is necessary to reduce the pitch P and the interval T, so it is necessary to reduce both of them to increase the density. had its limits.

[Problem that the invention seeks to solve]

The present invention was made under these circumstances, and it is possible to obtain a large delay time and good delay characteristics without reducing the pitch P and interval T of an inductance element formed in the shape of a single-layer solenoid. A small distributed constant type electromagnetic delay line is obtained.

[Means for solving problems]

In order to solve these problems, the electromagnetic delay line of the present invention has a conductive line formed into a substantially single-layer solenoid shape to constitute an inductance element, and a ground electrode is connected to the conductive line through a dielectric layer. are arranged to face each other, and capacitance compensation electrodes are extended from the sides of the conductive line at a plurality of locations to face the ground electrode.

[Effect]

By such means, the electromagnetic delay line of the present invention can be
It is possible to increase the inductance by narrowing the width of the conducting line, and to compensate for the lack of capacitance due to narrowing the width of the conducting line, or to compensate for the capacitance formed in the middle of the conducting line. Compensation electrodes facilitate compensation.

〔Example〕

Examples of the present invention will be described below.

1 and 2 are a partial front view and a side view of an embodiment of the electromagnetic delay line of the present invention.

In both figures, a dielectric layer 11 is formed on the outside of the thin and elongated ground electrode 9, and the dielectric layer 11 is formed into a flat bobbin on the outer periphery of the dielectric layer 11 with a width W.
A conductor strip 13 is formed in the shape of a single layer solenoid with a pitch P, and faces the ground electrode 9 with a dielectric layer 11 in between.

A plurality of L-shaped cuts 15 are formed from one side of the conductor strip 13 at regular intervals in the same direction. In other words, the rectangular electrode 19 extends from the side surface of the conductive path 17 having a width W' narrower than the width W via the narrow section 21.

The conductor strip 1 having a plurality of cuts 15 in this way
3, the high-frequency current flows exclusively through the conductive line 17, and this conductive line 17 functions as a conductor having an inductance, while each electrode 19 functions as a capacitance compensation electrode, which will be described later, between it and the ground electrode 9.

Since the conductor strip 13 is formed in the shape of a single-layer solenoid, the conductor line 17 is also formed in the shape of a single-layer solenoid, and the inductance element 23 facing the ground electrode 9 is configured to form a distributed electromagnetic delay line. It's summery.

Such an electromagnetic delay line is constructed by, for example, making the width W of the conductor strip 13 the same as that of the conventional conductor strip 5 and making the cut 15.
The electrode 19 is formed by the conductor strip 13.
When the conducting line 17 is formed to have a narrower width W', the inductance per unit length of the conducting line 17 increases.

Moreover, since the conductive line 17 has an electrode 19 extending from it, the capacitance of the conductive line 17 itself is small, but the capacitance due to the electrode 19 is added and the capacitance is compensated, and the conductive line 17 The delay time per unit length increases. That is, the electrode 19 functions as a capacitance compensation electrode.

Note that the characteristic impedance Zo of the conducting line 17 is
As mentioned above, it is determined by Zo=√, so it will be high.

Therefore, the pitch P and the interval T of the conductor line 17 are
It is easy to increase both the inductance and capacitance while keeping the conventional dimensions, increasing the delay time, improving the characteristics, and making it possible to reduce the size.

Of course, it is also possible, for example, to increase the width W of the conductor strip 13 to compensate for the capacitance that is more than the insufficient capacitance in the conductor line 17 with the capacitance compensation electrode 19, and in this case, a larger delay time can be used. is obtained.

In this regard, in the conventional example, both the inductance and the capacitance of the conducting line 5 were related to its width W, so there was a low degree of freedom in selecting dimensions when designing the electromagnetic delay line. However, in the present invention, the conducting line 17
width W' and the conductor strip 13 forming this conductor line 17.
Since the width W can be selected independently, the degree of freedom in design is increased.

Next, other embodiments of the present invention will be shown. FIGS. 3 and 4 are a front view and a sectional view showing another embodiment of the present invention.

Two thin dielectric plates 27 sandwiching the ground electrode 25
A plurality of elongated unit conductors (hereinafter referred to as upper surface side unit conductors) 31 are formed in parallel at a pitch P on the upper surface of the three-layer printed substrate 29 in which layers a and 27b are stacked. Note that the printed substrate 29 shows the minimum necessary part for explaining the embodiment.

One end of each upper unit conductor 31 (upper side in the figure) is a first connection part 31a, and the other end of each upper unit conductor 31 (lower side in the figure) is a second connection part 31a.
The connecting portion 31b is connected to the connecting portion 31b.

In each of the upper unit conductors 31, an L-shaped notch 33 is formed from the side surface near the first connecting portion 31a, and the tip of this notch 33 extends to the vicinity of the second connecting portion 31b. Top side unit conductor 3
1, a conductive line 35 having the same function as the conductive line 17 shown in FIG.
It is extended from the second connecting portion 31b.

On the lower surface of the printed circuit board 29, a plurality of unit conductors (referred to as lower surface unit conductors) 37 having the same width as the upper surface side unit conductor 31 are connected to the first connecting portion 31a of the upper surface side unit conductor 31 and the adjacent upper surface. It is formed obliquely with respect to the upper surface side unit conductor 31 so as to connect between the second connecting portions 31b of the side unit conductor 31. Although not shown in detail, a capacitance compensation electrode is formed on the lower unit conductor 37 as well as on the upper unit conductor 31.

One end of the lower unit conductor 37 (upper side in the figure)
serves as a first connecting portion 37a and faces so as to overlap with the first connecting portion 31a of the upper unit conductor 31, and the other end (lower side in the figure) of the lower unit conductor 37 is A second connection portion 37b similar to the first connection portion 37a faces and overlaps with the second connection portion 31b of the upper unit conductor 31.

The printed substrate 29 has, as shown in FIG.
A first connecting portion 31a of each upper unit conductor 31 and a first connecting portion 37a of each lower unit conductor 37,
Through holes 39 are formed so as to penetrate through the second connecting portion 31b of the upper unit conductor 31 and the second connecting portion 37b of the lower unit conductor 37, respectively.
Each through-hole 39 is connected to opposing first connecting portions 31a and 37a and second connecting portions 31b and 37b through a through-hole plating portion 41.

Therefore, the printed circuit board 29 has a single-layer solenoid-shaped inductance element 43 in which the upper unit conductors 31 and the lower unit conductors 37 are alternately connected in series.
The inductance element 43 faces the ground electrode 25 via the dielectric plates 27a and 27b to form a distributed constant electromagnetic delay line.

Note that the ground electrode 25 is connected to the through-hole plated portion 4.
It is formed so that it does not come into contact with 1.

By the way, the method of forming the capacitive compensation electrode in the electromagnetic delay line of the present invention is not limited to the above-mentioned method, and may be any method.

For example, although not shown, it is possible to achieve the object of the present invention by forming a straight cut in place of the L-shaped cut 15 in the embodiment shown in FIG. To ensure this, it is preferable to narrow the interval between the linear cuts.

In order to increase the inductance of the conductive line 17 beyond a certain level while suppressing the inductance of the capacitive compensation electrode, as shown in FIG. However, it is considered that a more favorable effect can be obtained by forming the capacitance compensation electrode through the narrow part.

Furthermore, the capacitance compensation electrode is not limited to being formed on one side of the conductive line. As shown in FIG. 6, L-shaped and linear cuts 15 and 49 may be formed alternately from both sides of the conductor strip 13 to form the conductive line 51 and the capacitive compensation electrode 53. In this case, the length of the conducting line 51 also becomes longer, and its inductance increases further.

Further, in each of the embodiments described above, the cuts 15, 33, 45,
Although an example has been shown in which the capacitance compensation electrodes 19, 36, and 53 are formed using the capacitance compensation electrodes 19, 36, and 53, in the present invention, it is sufficient that the capacitance compensation electrodes are formed extending from the conductive line, and any method of forming the capacitance compensation electrodes may be used. What is the conductive line of the present invention?
This refers to the part where high-frequency current flows.

Even in the case of an inductance element, the conductive line 17 is not substantially formed in a single-layer solenoid shape by passing alternately through two opposing surfaces as in the embodiment shown in FIG. Any type of solenoid may be used as long as it is formed in the shape of a single-layer solenoid and faces the ground electrode with a dielectric layer interposed therebetween.

〔Effect of the invention〕

As explained above, in the electromagnetic delay line of the present invention, capacitance compensation electrodes are extended from multiple locations on the conductive path of the inductance element, so the width of the conductive path is narrowed to increase the inductance and compensate for the capacitance. without reducing the pitch P and interval T of the inductance element.
The delay time can be increased and the size can be reduced, and good characteristics can be obtained.

[Brief explanation of the drawing]

1 and 2 are a partial front view and a side view of an embodiment of the electromagnetic delay line of the present invention, and FIG.
4 and 4 are front views showing other embodiments of the electromagnetic delay line of the present invention, and sectional views taken along Y-Y in FIG. Figures 7 and 8 showing other examples of compensation electrodes are partial front views showing conventional electromagnetic delay lines. 1, 9, 25... Ground electrode, 3, 11... Dielectric layer, 5, 17, 35, 51... Conductive line, 7, 2
3, 43... Inductance element, 13... Conductor strip, 15, 33, 45, 49... Notch, 19,
36, 47, 53...capacitance compensation electrode, 27a, 2
7b... Dielectric layer (dielectric plate), 29... Printed circuit board, 31... Upper surface side unit conductor, 37... Lower surface side unit conductor.

Claims (1)

[Claims] 1. A distributed constant electromagnetic delay line in which a conductive line is formed substantially in the shape of a single-layer solenoid to constitute an inductance element, and a ground electrode is opposed to the conductive line via a dielectric layer. An electromagnetic delay line, characterized in that capacitance compensation electrodes are extended from a plurality of locations of the conductive path to face the ground electrode.