JPH047656A - Bit selective output port and output device - Google Patents

Abstract

PURPOSE:To reduce the burden of a microprocessor by providing a selection circuit inputting an input data signal and an output data signal and selecting and outputting one signal based on a bit selection instructing signal. CONSTITUTION:The data signal outputted from CPU 11 is inputted to a second holding circuit 15 from the selection circuit 16. When the value of output data is changed in terms of bit, CPU 11 transmits a bit pattern signal, a decoder 12 outputs a first holding signal, a first holding circuit 14 holds the bit pattern signal and outputs it to the selection circuit 16 as a bit selection signal. Then, CPU 11 outputs the value of data corresponding to the bit to be altered to a data bus 17, and the selection circuit 16 selects the value supplied from the data bus 17 or the value given from the second holding circuit 15 so as to generate the data signal. Thus, an arithmetic processing can be reduced in CPU 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an output port connected to a microprocessor, and particularly to a bit that changes the value of a data signal output from the microprocessor in bit units and outputs it to the outside. Regarding selective output ports.

[Prior Art] Conventionally, in this type of bit selection type output port, the value of a data signal outputted from a microprocessor to an output port is stored in a memory and then outputted to the outside. .

When changing only the value of a given bit in the value of the output data signal, the microprocessor reads the data from memory, masks the specified bit to be changed, and assigns the value to be changed to the masked bit. In addition, it is output to the output port again, stored in memory, and output to the outside from the output port.

[Problems to be Solved by the Invention] However, with conventional bit-selective output ports, the microprocessor must perform many tasks such as calling data, masking predetermined bits, changing the data value of the masked bits, and re-outputting the changed data. There is a problem in that it has to be processed.

The present invention aims to provide a bit-selective output port that reduces the burden on the microprocessor.

[Means for Solving the Problems] According to the present invention, the value of a data signal that is connected to a microprocessor via a data bus and inputted from the microprocessor via the data bus is converted in bit units as necessary. a bit selection type output port that outputs a bit pattern signal inputted via the data bus as an output signal; a first holding circuit that outputs the input data signal and the output data signal manually, selects one of the signals bit by bit based on the bit selection instruction signal, and outputs the selected data signal. A bit selection comprising: a selection circuit; and a second holding circuit that holds a selected data signal in response to a second holding signal from the microprocessor and outputs the output data signal. A shaped output port is obtained.

Further, according to the present invention, there is provided an output device in which a microprocessor and a bit selection type output port are connected by a data bus and a control line, wherein the microprocessor sends a data signal and a bit pattern signal to the data bus. comprising means for outputting first and second holding signals to control lines at predetermined timings, the bit selection type output port holding the bit pattern signal in response to the first holding signal, A first holding circuit that outputs a bit selection instruction signal, receives the data signal and the output data signal from the bit selection type output port, and selects one of the signals on a bit-by-bit basis based on the bit selection instruction signal. a selection circuit that selects and outputs the selected data signal;
and a second holding circuit that holds the selected data signal in response to a second holding signal from the microprocessor and outputs it as a modified output data signal. .

[Example] The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention.

The output device of this embodiment includes a central processing unit (hereinafter referred to as CPU) 11 as a microprocessor, a decoder 12, and a bit selection type output processor 13.

Further, the bit selection type output processor 13 includes a first holding circuit 14 , a second holding circuit 15 , and a selection circuit 16 .

The CPU II, the first holding circuit 14, and the selection circuit 16 are connected by a data bus 17.

Further, the CPUI 1 and the decoder 12 are connected by an address bus 18 and a control signal line 19, and the decoder 1
2 are connected to the first and second holding circuits 14.15 by control lines 20.21, respectively.

The operation of this output device will be explained below.

CPU 11 sends a data signal or a bit pattern signal to data bus 17. Further, the CPU 1l sends an address signal selectively specifying either the first or second holding circuit to the address bus 18 and a control signal to the control signal line 19.

The decoder 12 controls the first and second holding circuits 14 and 15 according to a control signal from the CPU II.

The data signal output from the CPU II is input to the bit selection type output port 13. Bit selection type output port 1
The data signal input to the selector 3 is first input to the selection circuit 16. When no signal is input from the first holding circuit 14, the selection circuit 16 inputs the data signal as is to the second holding circuit 15.

The second holding circuit 15 holds the data signal in response to the holding signal from the decoder 12 and outputs it to the outside.

Next, the output data from the bit selection type output port 13 (
A case will be described in which the value of data held in the second holding circuit is changed bit by bit.

The CPU 11 sends a bit pattern signal specifying a bit whose data value is to be changed to the data bus 17, and sends an address signal and a control signal to the decoder 12 so as to output a first holding signal.

The first holding circuit 14 receiving the first holding signal holds the bit pattern signal. This bit pattern signal is then output to the selection circuit 16 as a bit selection signal.

Next, the CPU 1 inputs the data value corresponding to the bit to be changed to the selection circuit 17. Here, selection circuit 1
A data signal held by the holding circuit 14 is input to 7.

In accordance with the bit selection instruction signal, the selection circuit 16 selects the value supplied from the data bus 17 for bits for which there is an instruction, and the value provided from the second holding circuit 15 for bits for which there is no instruction. Create selected data signals. This selected data signal is transmitted to the data bus 17.
becomes a data signal with the same number of bits.

This selected data signal is sent to the second holding circuit 15, held by the holding signal from the decoder 12, and outputted to the outside as a changed data signal.

In this way, the CPU 11 sends a bit pattern signal indicating the bit to be changed and its value to the data bus 17, and sends a signal to the decoder 12 to output the first and second hold signals at predetermined timing. You can change the value of a data signal bit by bit just by sending .

[Effects of the Invention] According to the present invention, a bit selection type output port holds a bit pattern signal inputted from a CPU via a data bus in response to a first holding signal from the CPU, and outputs a bit selection instruction. A first holding circuit that outputs a signal, receives the input data signal and the output data signal, selects one of the signals in bit units based on the bit selection instruction signal, and outputs the selected data signal. and a second holding circuit that holds the selected data signal in response to a second holding signal from the CPU and outputs a changed output data signal. Value can be changed.

Thereby, the calculation processing of the CPU can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 11... Central processing unit, 12... Decoder, 1
3... Bit selection type output port, 14... First holding circuit, 15... Second holding circuit, 16... Selection circuit, 17... Data bus, 18... Address bus ,
19... Control signal line, 20... First control line, 21
...Second control line.

Claims (1)

[Claims] 1. An output port that is connected to a microprocessor via a data bus, holds an input data signal input from the microprocessor via the data bus, and outputs it as an output data signal. , a bit selection type output port that changes the value of the output data signal bit by bit as necessary and outputs it as a changed output data signal, the bit pattern signal input via the data bus being output from the microprocessor; a first holding circuit that holds in response to a first holding signal and outputs a bit selection instruction signal; and a first holding circuit that receives the input data signal and the output data signal, and based on the bit selection instruction signal in bit units. a selection circuit that selects one of the signals and outputs the selected data signal; and a selection circuit that holds the selected data signal in response to a second holding signal from the microprocessor and outputs the changed output data signal. A bit selection type output port, comprising: a second holding circuit that holds the bit. 2. An output device in which a microprocessor and a bit selection type output port are connected by a data bus and a control line, wherein the microprocessor sends a data signal and a bit pattern signal to the data bus and a first bit pattern signal to the control line. and means for outputting a second holding signal at predetermined timings, and the bit selection type output port holds the bit pattern signal in response to the first holding signal and outputs a bit selection instruction signal. a first holding circuit that outputs, the data signal and the output data signal from the bit selection type output port are input, and one of the signals is selected bit by bit based on the bit selection instruction signal. A selection circuit that outputs a data signal; and a second holding circuit that holds the selected data signal in response to a second holding signal from the microprocessor and outputs it as a modified output data signal. An output device characterized by: