JPH047668A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To execute a processing at high speed by operating 2<n>-number of processing elements in parallel and executing a one-dimensional orthogonal transformation. CONSTITUTION:A circuit consists of 2<n>-number (n >=2) of processing elements 1a-1d executing one-dimensional inverse orthogonal transformation, a storage element 2 connected to the processing elements 1a-1d and a control element 3 controlling the processing elements 1a-1d and the storage element 2. Data before two-dimensional orthogonal transformation are inputted to the processing elements 1a and 1b in the order of rows, intermediate data to which the one- dimensional orthogonal transformation of the rows is executed in the processing elements 1a and 1b are accumulated in the storage element 2. Then, intermediate data are read from the storage element 2 for respective rows and are inputted to the processing elements 1c and 1d. Namely, they can be operated in parallel. Thus, two-dimensional orthogonal transformation can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that performs two-dimensional orthogonal transformation (inverse orthogonal transformation).

[Conventional technology]

Orthogonal transformation is used in a number of fields as a signal processing method. For example, discrete cosine transform (hereinafter abbreviated as DCT) is used for compression processing of image data. Orthogonal transforms can be defined for multidimensional arrays, and the image data compression applications described above use a two-dimensional DCT. Since multidimensional orthogonal transformation requires a large amount of calculation, it is often processed by dedicated nodeware.

As an example of the configuration of a dedicated processing device used in this manner, there has been a conventional one of the type shown in FIG.

In (-) of FIG. 3, which is a block diagram showing an example of a semiconductor integrated circuit that is a device that performs a conventional two-dimensional orthogonal transform (inverse orthogonal transform), 11 is a processing element, which performs a one-dimensional orthogonal transform. do. 2 is a storage element, which is used to store intermediate results. 3 is a control element, which controls the processing element 11 and the storage element 2; The data before the two-dimensional orthogonal transformation is input to the processing element 11, and the data after the two-dimensional orthogonal transformation is also output from the processing element 11.

There is also a dedicated processing device of the type shown in FIG. 3(b), which is different from the type shown in FIG. 3(-).

In FIG. 3(b), the same symbols as in FIG. 3(a) indicate corresponding parts, 1j is a processing element that performs one-dimensional orthogonal transformation of rows, and 1 is a processing element that performs one-dimensional orthogonal transformation of columns. is an element. Then, the data before orthogonal transformation is processed 1! The data is input to the element 1j, and the data after orthogonal transformation is output from the processing element 1k.

In FIG. 3(&), data is exchanged between the processing element 11 and the storage element 2, and in FIG. 3(b), data is sent from the processing element 1j to the storage element 2, and from this storage element X2. Data is sent to processing element 1.

Next, the operation will be explained.

As is well-known, two-dimensional orthogonal transformation is performed in every row and every two columns.
#) can be performed by dimensional orthogonal transformation. Hereinafter, the orthogonal transformation will be explained using DCT as an example. 2
The dimensional DCT can be executed by decomposing it into a one-dimensional DCT with two rows and two columns.

In FIG. 3(a), the input data is processed by processing element 1.
1, one-dimensional OCT is performed for each row. The intermediate data subjected to row DCT is then sent to storage element 2 in batting order. The intermediate data stored in the storage element 2 is read out in column order, and the processing element 11 performs one-dimensional DCT on the column and outputs it. This completes the two-dimensional DCT processing.

In the case of FIG. 3(a), the processing element 11 executes row conversion and column conversion in a time-sharing manner, but in the case of FIG. 3(b), a different process is performed in the processing element 1j. 1st dimension D of rows
CT is performed, and one-dimensional DCT of the column is performed at processing point X1k.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit that performs two-dimensional orthogonal transformation (inverse orthogonal transformation) as described above has a problem in that the processing speed is insufficient when it is necessary to perform two-dimensional orthogonal transformation at high speed. This issue will be explained below.

To perform a two-dimensional DCT of N×N points, N row transformations and N
Since the column transformation is required t times, and N2 product-sum operations are required to calculate the N-point one-dimensional DCT, a total of 21 times is required.
This requires multiple product-sum operations.

In the case of FIG. 3(a), the processing element 11 performs the product-sum operation 2N'' times, and in the case of ) of FIG. 3, the processing element performs N!
This results in multiple product-sum operations.

Therefore, in order to perform two-dimensional DCT at high speed, the only way is to improve the performance of the processing elements, which has a technical limit.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit that can perform two-dimensional orthogonal transformation (inverse orthogonal transformation) at high speed without attempting to improve the performance of processing elements.

[Means to solve the problem]

A semiconductor integrated circuit according to the present invention includes 2n (n≧2) processing elements that perform a one-dimensional orthogonal transformation, a storage element connected to the processing elements, and a semiconductor integrated circuit that performs a two-dimensional orthogonal transformation. It is composed of a processing element and a control element that controls the storage element.

Further, a semiconductor integrated circuit according to another invention of the present invention includes 2
In a semiconductor integrated circuit that performs a dimensional inverse orthogonal transform, 2n (n≧2) processing elements that perform a one-dimensional inverse orthogonal transform;
A storage element connected to this processing element, said processing element and said storage! ! and a control element for controlling the elements.

[Effect]

In this invention, 21 processes I! By operating the elements in parallel and performing one-dimensional orthogonal transformation (inverse orthogonal transformation),
Enables high-speed processing.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. Note that the case where n=2 is taken as an example.

FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention.

In the figure, 11 to 1d are processing elements that each perform a one-dimensional orthogonal transformation, and 2 is a storage element connected to these processing elements 11 to 1d, which stores intermediate data during processing. Reference numeral 3 denotes a control element that controls the processing elements 1a to 1d and the storage element 2.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the data before two-dimensional orthogonal transformation is processing element 11.1b
are entered in batting order. And processing elements 1a, Ib
The intermediate data subjected to the one-dimensional orthogonal row transformation is stored in the storage element 2.

Next, the intermediate data is read column by column from the storage element 2 and input to the processing elements 1c and ld. Here, the output data subjected to the one-dimensional orthogonal transformation in the example results in the two-dimensional orthogonal transformation result of the input data. As mentioned earlier,
A two-dimensional orthogonal transformation of NxN points can be performed by a one-dimensional orthogonal transformation of N rows and a one-dimensional orthogonal transformation of N columns, so the processing element 1m+1b is a one-dimensional orthogonal transformation of N/2 rows. The processing element 1C21d only needs to perform one-dimensional orthogonal transformation of columns N/2 times.

For example, if we consider the case of performing 8-point x 8-point two-dimensional OCT, for example, the processing element 1a is the one-dimensional DC in the first to fourth rows.
T, the processing element 1b executes the one-dimensional DCT of the fifth to eighth rows on the input data, and the processing element 1c executes the one-dimensional DCT of the first to eighth rows.
1D OCT of columns ~ 4th column wo, processing required $1d is ag5
The one-dimensional DCT of the columns to the eighth column will be executed on the intermediate data, respectively.

In the above embodiment, the processing elements 1a and 1b are used for orthogonal transformation of rows, and the processing elements 1c and 1d are used for orthogonal transformation of columns, but the configuration shown in FIG. 1 can be used for processing! ! It is also possible to use the elements 1a and 1b for column orthogonal transformation, and the processing elements 1e and Id for row orthogonal transformation.

In FIG. 1, data is sent from processing elements 1B and 1b to storage element 2, and from this storage element X2 to processing element 1c.
, ld.

Further, as shown in Fig. 82 showing another embodiment of the present invention, 4
It is also possible to adopt a configuration in which two processing elements are used for orthogonal transformation of rows and columns.

In the figure, 1@ to 1h are processing elements that execute one-dimensional orthogonal transformation, and execute orthogonal transformation of p rows or columns under the control of control@element 3. 2 is a storage element connected to the processing elements 16 to 1h.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

Input data is input to processing elements 1s and 1h in batting order, and is subjected to one-dimensional orthogonal transformation of the rows. The resulting intermediate data is once stored in the storage element 2 in batting order, and then read out in column order and subjected to one-dimensional orthogonal transformation of the columns in processing elements 10 to 1h. As a result, the data obtained is the result of two-dimensional orthogonal transformation of the input data of the element. Also in the embodiment shown in FIG. 82, the order of row processing and column processing may be reversed.

In FIG. 2, data is exchanged between each of the processing elements 1e to 1h and the storage element 2.

In this way, all 2n processing elements are controlled! ! It is controlled from the top and is configured to perform one-dimensional orthogonal transformation of all rows at a certain time, and to perform one-dimensional orthogonal transformation of columns at a certain time.

Further, among the 21 processing elements, half of the processing elements always perform one-dimensional orthogonal transformation of rows, and the remaining half of the processing elements always perform one-dimensional orthogonal transformation of columns. In addition, the orthogonal transform is the discrete cosine transform (DCT)
It is.

In the above embodiment, a device that performs two-dimensional orthogonal transformation has been described, but by constructing this device using a semiconductor integrated circuit, it is possible to reduce the size and cost of the device and improve its performance. can.

Further, in the above embodiment, the processing to be performed was a two-dimensional orthogonal transformation, but it is also possible to perform a two-dimensional inverse orthogonal transformation with the configuration of the transformation circuit shown in FIGS. 1 and 2. In this case, the processing elements 1a to 1a shown in FIGS.
The processing performed by 1h is simply one-dimensional inverse orthogonal transformation.

That is, 2n (n≧2
), a storage element connected to the processing elements 1 & ~1h, and a control element that controls the processing element and the storage element.

The 2n processing elements are all controlled by the control element, and are configured to perform one-dimensional inverse orthogonal transformation of rows at a certain time, and perform one-dimensional inverse orthogonal transformation of columns at a certain time. There is. Furthermore, among the 21 processing elements, the semiconductor processing elements are configured to always perform one-dimensional inverse orthogonal transformation of rows, and the remaining half of the processing elements are configured to always perform one-dimensional inverse orthogonal transformation of columns. There is. Further, the orthogonal transform is configured to be an inverse discrete cosine transform (DCT).

In this way, the processing performed by the processing element is simply a one-dimensional inverse orthogonal transformation. In this case as well, the same effect as the above-mentioned embodiment regarding two-dimensional orthogonal transformation can be achieved.

〔Effect of the invention〕

As described above, this invention is configured to have 2n (n≧2) processing elements that perform one-dimensional orthogonal transformation (inverse orthogonal transformation) and to operate in parallel, so that it can perform two-dimensional This has the effect of making it possible to perform orthogonal transformation (inverse orthogonal transformation).

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of a semiconductor integrated circuit according to the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, and Fig. 3 is a conventional two-dimensional orthogonal transform (inverse orthogonal transform). 1 is a block diagram illustrating an example of a semiconductor integrated circuit that performs. 1a to 1d, is to 1h...processing elements, 2...
...Storage element, 3...Control element.

Claims (2)

[Claims] (1) In a semiconductor integrated circuit that performs two-dimensional orthogonal transformation,
It is composed of 2n (n≧2) processing elements that execute one-dimensional orthogonal transformation, a storage element connected to this processing element, and a control element that controls the processing element and the storage element. Features of semiconductor integrated circuits. (2) In a semiconductor integrated circuit that performs a two-dimensional inverse orthogonal transformation, there are 2^n (n≧2) processing elements that perform a one-dimensional inverse orthogonal transformation, a storage element connected to these processing elements, and a memory element connected to the processing element. 1. A semiconductor integrated circuit comprising: an element; and a control element that controls the storage element.