JPH0476888A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the generation of the malfunction of a circuit by providing an address signal change detecting circuit at an address signal inputting circuit due to the generation of a noise, and removing a noise signal during the generation of the noise by a latch circuit controlled by the signal of the address signal change detecting circuit. CONSTITUTION:This device is equipped with an address signal change detecting circuit ATD which inputs the output of an address signal inputting circuit AC0 and generates a detection pulse 2 by the change of the address. While this circuit ATD is in an H level including a noise voltage vN generating period TN, an inverter INV1 with a latch is controlled by an ATD signal 2. Thus, a sense amplifier outputting signal 1 including the noise voltage vN is not fetched, the ATD signal 2 rises after a point of time t2 in which the noise is recovered, and the correct data is fetched from a Y-selector in an inverter INV1. An output data which is not affected by the noise, is outputted through a data outputting circuit DOS to OUT, at a point of time t3 after that. Thus, the malfunction of the circuit can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an asynchronous semiconductor memory device.

[Conventional technology]

Conventionally, circuit operations of semiconductor memory devices include an asynchronous type and a synchronous type, and in one type of asynchronous type circuit, various circuits change according to changes in an address signal and output data.

This asynchronous type circuit is widely used because it does not require timing adjustment from the basic signal and can easily speed up the basic circuit, and is easy to design.

The other synchronous operation circuit uses a signal generated by a change in the address signal as a basic signal, latches the address signal, operates various circuits sequentially, latches the data output signal, and holds it until the next change in the address signal. .

FIG. 3 is a block diagram of an example of a conventional semiconductor memory circuit, and FIG. 4 is a signal timing diagram of each part of the block in FIG.

In FIGS. 3 and 4, the current address input signal terminal A
If a noise from "H" to "L" occurs after the sense amplifier 4 changes from "L" to "H" at time t1 due to the signal of "O", the output signal 1 of the sense amplifier 5 has a vN malfunction. The waveform is output and the subsequent data output circuit D
A similar malfunction waveform N is output to OUT via OC,
Holding of the "'H°" level is temporarily interrupted, and the rising speed of the output signal is effectively delayed.

[Problem to be solved by the invention]

However, in conventional asynchronous operation circuits, various circuits operate according to changes in the address signal to change the data output, so a noise signal is generated in the power supply and GND due to the instantaneous large current caused by the data output change, and the noise signal is This has the disadvantage that it is easily fed back to the address input signal circuit or to the sense amplifier circuit, causing a malfunction as if the address signal or data in the sense amplifier circuit had changed.

[Means to solve the problem]

A semiconductor memory device according to the present invention inputs a plurality of address input signals and outputs read data of a memory cell via a sense amplifier and an inverter. The address input signal change detection circuit is configured to include at least one address input signal change detection circuit that supplies a predetermined pulse to the latch section of the inverter.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing diagram of each signal for explaining the operation of the blocks in FIG. 1.

AO and Al are address signal terminals, ACO and ACl are address signal input circuits, INVI is an inverter with a latch that latches data at the falling edge of the ATD signal, INV2 is an inverter, and poc is a data output circuit. This semiconductor memory device has an inverter IN of the semiconductor memory device shown in FIG.
The difference from the conventional example is that V3 is replaced with an inverter INVI with a latch, and an address signal change detection circuit ATD is provided which inputs the output of the address signal input circuit ACO and generates a detection pulse 2 according to a change in the address.

While the address signal change detection circuit ATD is at “H” level, which includes the period TN where noise vN occurs, the inverter I with latch is
NVI is controlled by ATD signal 2, and the noise voltage v
The sense amplifier output signal l containing N is not taken in, and after the time t2 when the noise has recovered, the ATD signal 2 falls, and the correct data is taken into the inverter INV1 from the Y-selector, and at the subsequent time t3. Data output circuit DOC
After that, output data that is not affected by noise is output to OUT.

Generally, noise generation due to address signals is often caused by a specific address signal, so it is sufficient to input a necessary sense amplifier signal to the ATD.

In addition, each address signal input terminal Act (i=1 to n)
It is also possible to provide an address signal change detection circuit ATD i between the sense amplifier 41 and each sense amplifier 41 to control their operation/non-operation.

〔Effect of the invention〕

As explained above, the present invention provides an address signal change detection circuit in an address signal input circuit caused by noise generation, and uses a latch circuit based on the signal to remove the noise signal during the noise generation period, thereby preventing malfunction of the circuit. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a block diagram of an example of a conventional semiconductor memory device, and FIG. 4 is a timing diagram of each signal to explain the operation of the blocks in FIG. 3. FIG. INVI...Inverter with latch, INV2゜INV
3...Inverter, AO, Al...Address signal terminal, ACI, ACI...Address signal power circuit, AT
D: Address signal change detection circuit, DOC: Data output circuit, OUT: Data output terminal.

Claims (1)

[Claims] 1. In a semiconductor memory device that inputs a plurality of address input signals and outputs read data of a memory cell via a sense amplifier and an inverter, the address input signal is input and the read data of a memory cell is outputted. A semiconductor memory device comprising at least one address input signal change detection circuit that supplies a predetermined pulse to a latch section of the inverter. 2. A claim characterized in that the address change detection circuit is provided in correspondence with each address input signal, and includes control means that can select use or non-use of the address change detection circuit for each address signal. 2. The semiconductor memory device according to item 1.