JPH047760A - High speed memory access system - Google Patents

Abstract

PURPOSE:To attain a high speed memory access for a microprocessor with use of an inexpensive controller by providing a data store part, an address control part, and an address comparing part. CONSTITUTION:A data store part 4 stores the data read out of a memory part 5. An address control part 2 stores the memory data read address to be sent to a memory part 5 and then counts up this read address when the read data are stored in the part 4. An address comparing part 3 compares the memory data read address given from a microcomputer 1 with the memory data read address stored in the part 2. When no equal comparison occurs between both addresses, the memory data read address received from the microprocessor 1 is stored in the part 2. Thus the memory access is attained at a high speed for the microprocessor by means of an inexpensive controller.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed memory access method in a control device having a microprocessor and an associated memory section.

[Conventional technology]

Conventionally, as this type of high-speed memory access method, there has been a method using Canon memory.

(IO to be solved by the invention) In the conventional high-speed memory access method using the conventional cassette memory described above, an expensive high-speed memory must be used as the cassette memory, and furthermore, a dedicated controller for the cassette memory is required. Therefore, there is a drawback that the control device to which the high-speed memory access method is applied becomes a very expensive control device.

In view of the above points, an object of the present invention is to provide a high-speed memory access method that can speed up the memory access of a microprocessor using an inexpensive control device and improve the processing performance of the microprocessor. be.

[Means to solve the problem]

The memory high-speed access method of the present invention provides a control device having a microprocessor and an associated memory section, which includes a data storage section that accumulates read data read from the memory section, and a memory data read address that is sent to the memory section. an address control section that counts and amplifies a memory data read address to be sent to the memory section at the time when the read data is accumulated in the data storage section; and an address comparison section that compares the memory data read address from the microprocessor and stores the memory data read address from the microprocessor in the address control section if the two do not match.

[Effect]

In the memory high-speed access method of the present invention, the data storage section stores the read data read from the memory section, the address control section stores the memory data read address to be sent to the memory section, and the read data is stored in the data storage section. The address comparator counts and amplifies the memory data read address sent to the memory unit at the time when the memory data read address from the microprocessor is stored in the memory data read address stored in the address control unit. If they do not match, the memory data read address from the microprocessor is stored in the address control section.

〔Example〕

Next, the present invention will be explained with reference to a concave surface.

FIG. 1 is a block R showing the configuration of an embodiment of the memory high-speed access method of the present invention. The high-speed memory access system of this embodiment includes a microprocessor 1, an address control section 2, an address comparison section 3, a data storage section 4, and a memory section 5.

FIG. 2 is a time chart showing an overview of an example of the operation of the memory high-speed access method of this embodiment.

Next, the operation of the memory high-speed access system of this embodiment configured as described above will be explained.

When reading memory data, the memory data read address from the microprocessor 1 is sent at a fixed interval (an interval of one bus cycle which is a fixed number of operating clocks of the microprocessor 1. In the example of FIG. 2, the interval is T1 to T4. (wait cycle TW may be inserted).

On the other hand, the memory data read address stored in the address control section 2 is sent from the address control section 2 to the memory section 5 .

The present embodiment (and thus the present invention) is applied to memory data read where the memory data read address from the microprocessor I is often counted and amplified continuously (increasing the memory data read address by one unit). (using instruction word reading as a typical example,
This kind of memory data reading is common)
.

In this way, when the memory data read address from the microprocessor 1 is continuously counted up, the memory data read address stored in the address control unit 2 is
The value is obtained by pre-fetching the value of the memory data read address from the microprocessor 1, and when the memory data read signal (RD) from the microprocessor 1 falls (at the time when the signal instructing the memory data read is issued), both memory data are read. The addresses will have the same value.

Now, when the memory data read signal from the microprocessor 1 falls (the memory data read signal is a negative logic signal, a low state indicates a memory read instruction), the memory data read address from the microprocessor 1 is and the memory data read address stored in the address control section 2 are compared by the address comparison section 3.

As mentioned above, in this comparison, the two are in principle consistent.

If the two match in this way, the state is not changed (the memory data read address stored in the address control unit 2 continues to be sent to the memory unit 5 as before).

Data (memory data) is read from the memory unit 5 based on the memory data read address and the memory data read signal (MEMRD) from the address control unit 2.
is read out. The data is stored in the data storage section 4 as read data.

For the read data stored in the data storage section 4,
A data read process (a process of reading out read data stored in the data storage section 4) is performed by the microprocessor 1.

On the other hand, when the read data is stored in the data storage section 4, the memory data read address stored in the address control section 2 is counted and amplified, and the memory data read address after the count amplification is newly stored in the memory section 4.
will be sent to.

Based on the memory data read address after the count amplifier sent out in this way, the next data is read from the memory section 5, and the read data is transferred to the data storage section 4.
is stored as read data.

Therefore, before the memory data read address is sent from the microprocessor 1, the address control section 2 sends the memory data read address to the memory section 5, and the memory access by the microprocessor 1 becomes faster.

For example, the memory data read address rn+ in FIG.
2 (n is a positive integer), the time t when the read data related to the previous memory data read (memory data read based on the memory data read address rn+IJ) was accumulated in the data storage section 4.
2, the memory data read address stored in the access control unit 2 is incremented, and the counted up memory data read address "n+" is counted up.
2'' is sent to the memory section 5. At this time t2, the memory data read address rn is read from the microprocessor 1.
This is an earlier time than the time t3 at which +2J is sent. Therefore, the read data related to the memory data read address "n+2" is already accumulated in the data storage section 4 at time t4, and the memory access by the microprocessor 1 becomes faster.

Exceptionally, the memory data read address from the microprocessor 1 is not counted up continuously, and the address comparison unit 3 compares the memory data read address from the microprocessor 1 with the memory stored in the address control unit 2. If the data read address does not match, the address comparison section 3 notifies the address control section 2 of this fact.

Based on this notification, the address control section 2 newly stores the memory data read address from the microprocessor 1 as the memory data read address to be sent to the memory section 5.

Therefore, the memory data read address that has already been sent to the memory unit 5 at that point is canceled, the newly accumulated memory data read address is sent to the memory unit 5, and the memory data read address is sent to the memory unit 5 based on the memory data read address. Data is read from 5.

For example, memory data read address rnJ in FIG.
In the memory data read based on the memory data read address rnJ, the memory data read address 1m (m is a positive integer not n) is different from the memory data read address rnJ at time t1, and the memory data read address rmJ that had been sent to the memory unit 5 until then is different from the memory data read address rmJ. is canceled, and memory data is read using the memory data read address rnJ.

In this way, when reading memory data, in principle, the memory data read address from the microprocessor 1 is continuously counted up, but in exceptional cases, when the memory data read address is not counted up continuously, It becomes possible to speed up memory access by the microprocessor 1 while also dealing with the above problems.

〔Effect of the invention〕

As explained above, the present invention speeds up memory access of a microprocessor with an inexpensive control device that does not use expensive hardware such as a cache memory by providing a data storage section access control section and an address comparison section. This has the effect of improving the processing performance of the microprocessor.

The above-mentioned effect is particularly significant when reading command words, where the memory data read address is often counted up continuously.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing an overview of an example of the operation of the memory high-speed access method shown in FIG. In the figure, 1... microprocessor, 2... address control section, 3... address comparison section, 4... data storage section, 5... memory section.

Claims (1)

[Claims] A control device having a microprocessor and an associated memory unit, comprising: a data storage unit that stores read data read from the memory unit; and a memory data read address that stores memory data read addresses to be sent to the memory unit. , an address control unit that counts up a memory data read address to be sent to the memory unit when the read data is accumulated in the data storage unit; and a memory data read address from the microprocessor and the memory data read address stored in the address control unit. 1. A high-speed memory access system, comprising: an address comparison section that compares a memory data read address and stores a memory data read address from a microprocessor in the address control section if the two do not match.