JPH0477926A - Fuzzy inference arithmetic circuit - Google Patents

Abstract

PURPOSE:To save the capacity of a storage part and to reduce the area of this circuit by taking a difference value between adjacent vector element data through the use of strong correlation between adjacent vector element data in a membership function and effectively data-compressing and storing a membership function vector. CONSTITUTION:An operation part 2 calculates the difference value between the adjacent vector element data of the membership function vector obtained by a fuzzy inference operation. The storage part 1 stores the difference value calculated in the operation part 2 as information indicating the membership function vector. Correlation between adjacent vector element data of the membership function in fuzzy inference is strong and the membership function vector can effectively data-compressed by taking the difference value between adjacent vector element data. Thus, information in a data compressed form is stored and the capacity of the storage part 1 can be saved. Thus, the area of the circuit can effectively be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fuzzy inference arithmetic circuit that performs fuzzy inference arithmetic processing using membership function vectors expressed as discrete values.

[Prior Art] Conventionally, this type of fuzzy inference arithmetic circuit connects a data storage section 1 and an inference arithmetic unit 2 via a data bus 3, as shown in FIG. It is configured to include a data transfer control section (not shown) that controls data transfer to and from the inference calculator 2.

The data storage unit 1 stores membership function vectors for performing inference calculations. The inference calculator 2 sequentially reads each element data of the membership function vector from the data storage unit 1 via the data bus 3 and executes a predetermined inference operation.

The membership function stored in the data storage unit 1 is the seventh
As shown in the figure, it is a function that shows gradual changes, and is stored in the form of vector element data expressed as discrete values. FIG. 8 shows each element data Y of the membership function vector stored in the data storage unit 1. It is a figure showing yN-t. Usually, the order of this membership function vector exceeds several tens of orders, and each element data Y. In order to have a certain degree of expression accuracy, ys-t is expressed with a data word length of, for example, about 8 bits.

[Problems to be Solved by the Invention] As mentioned above, the order of the membership function vector expressed as a discrete value exceeds several tens of orders, and the data word length of each vector element data also has a certain degree of representation accuracy. Since the number of bits is set to the number of bits obtained, in conventional fuzzy inference calculation circuits, the storage unit for storing the membership function vector requires a large capacity compared to the storage unit of other software, and the data storage There is a problem in that the area occupied by the circuit of the memory element forming the part increases.

To avoid this, reducing the storage capacity and importing necessary data from outside will increase the frequency of data transfer to and from the outside, reducing the time available for the calculation itself. There is a problem.

Furthermore, since the area occupied by the data bus connecting the data storage section and the inference calculation section in the circuit is also proportional to the data word length,
In conventional circuits, the area occupied by the data bus increases in order to obtain a predetermined representation accuracy, which also causes an increase in circuit area.

In particular, when multiple arithmetic units are operated in parallel on the same chip to speed up processing, the number of data buses connecting the storage section and the arithmetic section increases in proportion to the number of arithmetic units. Therefore, with the conventional data word length, there is a problem that the number of arithmetic units that can be installed in parallel is naturally limited.

The present invention has been made in view of such problems, and includes:
The capacity of the data storage section can be reduced without introducing data from the outside, and the bus width of the bus connecting the data storage section and the calculation section can be reduced.
It is an object of the present invention to provide a fuzzy inference arithmetic circuit that can significantly reduce the circuit area.

[Means for Solving the Problems] A fuzzy inference calculation circuit according to the present invention includes a storage section that stores information indicating a membership function vector, and uses the information indicating the membership function vector stored in this storage section. In the fuzzy inference calculation circuit, the calculation unit includes a calculation unit that performs fuzzy inference calculations, and a bus that connects the storage unit and the calculation unit. A difference value between adjacent vector element data is calculated, and the storage unit stores the difference value calculated by the calculation unit as information indicating the membership function vector.

Further, the fuzzy inference calculation circuit according to the present invention includes a storage section that stores information indicating a membership function vector, and performs a fuzzy inference operation using the information indicating the membership function vector stored in this storage section. In a fuzzy inference calculation circuit comprising an arithmetic unit and a bus connecting the storage unit and the arithmetic unit, the storage unit stores a difference value between adjacent vector element data of the membership function vector in the membership function vector. The information is stored as information indicating a vector, and the calculation unit reproduces each vector element data by adding the difference value read from the storage unit and the adjacent vector element data that has already been reproduced, and performs fuzzy inference. It is characterized by being used for calculations.

[Effect] In general, the correlation between adjacent vector element data of membership functions in fuzzy inference is strong, and membership function vectors can be effectively compressed by taking the difference value between these adjacent vector element data. can.

The same holds true for fuzzy inference calculation results using membership function vectors, and the correlation between adjacent vector element data does not drop significantly compared to before the calculation.

According to the present invention, information in a data compressed form is obtained by calculating the difference value between adjacent vector element data of the membership function vector obtained by the calculation unit, and this is stored in the storage unit. Therefore, the capacity of the storage section can be significantly reduced, and the width of the bus connecting the storage section and the arithmetic section can be reduced to the bus width of the compressed word length.

Note that the difference value read from the storage unit is added to the already reproduced adjacent vector element data, thereby being reproduced as each vector element data.

As described above, according to the present invention, the capacity of the storage section and the bus width can be significantly reduced, so that the circuit area can be effectively reduced.

[Embodiments] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a fuzzy inference calculation circuit according to a first embodiment of the present invention.

The data storage section 1 and the calculation section 7 are connected via a data bus 3. Transfer of data between the data storage section 1 and the calculation section 7 is performed by a data transfer control section (not shown).

The data storage unit 1 stores data indicating vector element data of membership functions as shown in FIG. This data is upper bit data Y of the value of the 0th element of the membership function vector shown in FIG. ■, similarly, the lower bit data Yot and the difference value between each adjacent element after the first element Y, Yo, Y2 Yl, "', Ys-1
It consists of YN-2. The data of the O-th element is used as initial data to give the absolute value of the membership function vector when reproducing the membership function vector. The reason why the data of the O-th element is divided into upper bits and lower bits is to match the number of bits with other difference values. Since each data after the first element is a difference value based on the correlation between adjacent elements of the membership function, it can be expressed with a small number of bits, for example, about 4 bits.

Therefore, each piece of data stored in the data storage unit 1 is expressed with half the number of bits as in the conventional case.

Therefore, the number of bits of data exchanged between the data storage section 1 and the arithmetic section 7 is small, and the data bus 3 connecting the two may also have a bit width of 4 bits.

On the other hand, the arithmetic unit 7 includes an inference arithmetic unit 2 and a bus interface 4. The bus interface 4 is arranged between the data bus 3 and the inference calculator 2, and includes a data expansion circuit 5 and a data compression circuit 6 that expand and compress data between the inference calculator 2 and the data storage unit 1. It is made up of.

The data decompression circuit 5 decompresses, for example, 4-bit compressed data read from the data storage unit 1 to produce 8-bit decompressed data and outputs it to the inference arithmetic unit 2. For example, as shown in FIG. , an adder 11 and a register 12. The adder 11 performs addition processing on successive data read from the data storage section 1 and expanded data stored in the register 12 and outputs the result to the register 12. This adder 11 is configured to input initial data in accordance with an initial data input control signal. The register 12 is set and reset by a set signal and a reset signal, respectively, and temporarily holds the calculation result of the adder 11 according to a latch signal.

The data compression circuit 6 compresses the 8-bit calculation result from the inference calculator 2 into 4-bit compressed data and outputs it to the data storage unit 1. For example, as shown in FIG. It is composed of a latch/register 13 and a subtracter 14. The data latch/register 13 is reset by a reset signal and latches the arithmetic unit output data output from the inference arithmetic unit 2 in accordance with the latch signal. Subtractor 14 has input latch/register 1
3 and the arithmetic unit output data to generate compressed data and output it.

Next, the operation of the fuzzy inference arithmetic circuit according to this embodiment configured as described above will be explained.

When read data from the data storage section 1 is input to the data expansion circuit 5, the data expansion circuit 5 converts the successive data into data Y of the first element. ③, the register 12 is reset and the data Y is inputted by the initial data input control signal.
. H9YoL is added by an adder 11 to generate initial data. Subsequently input data is added to the vector element data of the membership function vector that has been reproduced immediately before. The result of this addition is sent to register 1 in synchronization with the latch signal.
2 and is stored in the inference calculator 2 as decompressed data.
is output to. Note that if the adder 11 overflows during data expansion, a signal indicating the overflow is given to the register 2 as a set signal, so that the register 12 outputs limited data.

On the other hand, when the storage arithmetic unit output data of the inference result obtained by the inference arithmetic unit 2 is input to the data compression circuit 6, the data compression circuit 6 uses this data and the immediately preceding data stored in the input latch/register 13. A subtracter 14 calculates a difference value with adjacent vector element data. The result of this subtraction is then output to the data storage unit 1 as compressed data.

Note that if the calculation unit output data is initial data,
The distribution of the upper bits and lower bits of the arithmetic unit output data is processed by the initial data input control signal and the initial data output control signal.

As described above, according to the circuit of this embodiment, the number of bits of data stored in the data storage unit 1 is reduced by half by utilizing the strong correlation between adjacent elements of the membership function vector.
Therefore, the data capacity of the data storage unit 1 can be reduced to 1/2, and the bus width of the data bus 3 can also be reduced to 1/2.

FIG. 8 is a block diagram of a fuzzy inference calculation circuit according to a second embodiment of the present invention.

This embodiment is a diagram showing an example in which the present invention is applied to a system in which processing time is shortened by performing parallel processing by three calculation units 7a, 7b, and 7c.

That is, the calculation units 7a+ 7b+ 7c connect to the data storage unit 1a+ via the bus switch circuits 20a+20b, 20c and the data buses 3a+3b+3c, respectively.
1b and lc. Each calculation unit 7i (i is a+
1)+C; the same applies hereinafter) consists of an inference calculator 21 and a bus interface 41, and the bus interface 41 further includes a data decompression circuit 51 and a data compression circuit 6.
It is composed of 1. The configuration of these calculation units 71 is similar to that of the calculation unit 7 shown in FIG. 1, so detailed explanation thereof will be omitted.

The data storage units 1a to 1c store data indicating membership function vectors similar to those shown in FIG. 2 as differential values.

Further, the bus switch circuits 20a to 20c are connected by inter-operation block buses 21a and 21b,
A bus link is constructed through these.

In this embodiment, since a parallel calculation method is adopted, the number of data bus sets between the calculation units 7a to 7c and the data storage units 1a to 1c is increased compared to the first embodiment. By compressing the data between the sections 1a to 1c and the calculation sections 7a to 7c, it is possible to configure a parallel circuit with an extremely smaller wiring area than in the past.

[Effects of the Invention] As explained above, according to the present invention, by utilizing the strong correlation between each adjacent vector element data of the membership function,
Since the membership function vector is effectively compressed and stored by taking the difference value between adjacent vector element data, the capacity of the storage section can be significantly reduced, and the storage section and calculation section can be The width of the bus connecting the two can also be reduced in accordance with the compressed word length.

Therefore, the circuit area can be significantly reduced.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a fuzzy inference calculation circuit according to a first embodiment of the present invention, Fig. 2 is a schematic diagram showing stored data in a data storage section in the same circuit, and Fig. 3 is a block diagram of a data decompression circuit in the same circuit, FIG. 4 is a block diagram of a data compression circuit in the same circuit, FIG. 5 is a block diagram of a fuzzy inference calculation circuit according to the second embodiment of the present invention, and FIG.
Figure 7 is a block diagram of a conventional fuzzy inference calculation circuit, Figure 7 is a graph showing membership function vectors used in fuzzy inference calculation, and Figure 8 shows data stored in the data storage section in the conventional fuzzy inference calculation circuit. FIG.

Claims (2)

[Claims] (1) A storage unit that stores information indicating a membership function vector; an operation unit that performs a fuzzy inference operation using the information indicating the membership function vector stored in the storage unit; and an operation unit that performs an operation with the storage unit. In the fuzzy inference calculation circuit, the calculation unit calculates a difference value between adjacent vector element data of the membership function vector obtained by the fuzzy inference calculation, and the storage unit A fuzzy inference calculation circuit, characterized in that the difference value calculated by the calculation unit is stored as information indicating the membership function vector. (2) a storage unit that stores information indicating a membership function vector; an operation unit that performs a fuzzy inference operation using information indicating the membership function vector stored in the storage unit; and an operation unit that performs an operation with the storage unit. In the fuzzy inference calculation circuit, the storage unit stores a difference value between adjacent vector element data of the membership function vector as information indicating the membership function vector. The calculation unit reproduces each vector element data by adding the difference value read from the storage unit and the already reproduced adjacent vector element data and uses it for fuzzy inference calculation. Features a fuzzy inference calculation circuit.