JPH0477941A - Picture controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to an image control device that stores image data and controls display of the image.

[Prior Art] Conventionally, an image control device that stores image data and controls the display of the image has been configured as shown in FIG.

For the sake of explanation, it is assumed that the image data input/output unit of this image control device is 8 bits, and the image data is 1 pixel and 1 bit. Assuming that the beginning of the memory address of the memory unit 101 is address 0 (the address seen from the bus mask has an offset address added thereto), the image data having a two-dimensional matrix structure is as shown in FIG. , one row from address 0 of the storage unit 101 in the column direction every 8 pixels from the upper left corner,
The data is stored in order up to the col and end addresses. Next, the image data in the second line starts from the pitch address (pitch
+co1. end ) address is stored. Similarly, until the image data of the last row (row, end),
It is stored in the storage unit 101. Here, in general, pitc
h≧co1. It is end. Normally, in order to make it easier to handle addresses in software and to simplify peripheral circuits in hardware, a value that is a power of 2 (=2'') is used as the pitch value.

Therefore, as shown in Figure 12, the y-th row counting from 0,
The address of the storage section where the Xth data is stored counting from 0 in units of 8 pixels is (pitchX y +
) becomes the address. Defining the storage address like this,
The address for the storage unit generated by the display device control unit 102 can be obtained by simply connecting the respective outputs of a counter that counts in the horizontal direction and a counter that counts in the vertical direction, and no arithmetic circuit is required.

Next, a procedure for transmitting image data to a display device having, for example, a raster scan type CRT display (hereinafter referred to as CRT) will be explained. When displaying image data using the raster scan method, generally the CRT is scanned from left to right and displayed one pixel at a time, and when the right end is reached, it returns to the left end without displaying, and this is repeated one line at a time from top to bottom. The order is as follows. In such scanning, the timing of horizontal scanning is based on a horizontal synchronization signal (hereinafter referred to as H3YNC signal). While continuing scanning in the left and right direction, when the scanning reaches the bottom of the CRT, the scanning returns to the top of the CRT without displaying, and this process is repeated thereafter. The timing of this vertical scanning is based on a vertical synchronization signal (hereinafter referred to as a VSYNC signal). FIG. 13 schematically shows the state of this scanning. Further, in FIG. 13, solid lines indicate scanning while displaying, and dotted lines indicate scanning without displaying. FIG. 14 and FIG. 15 are block diagrams of the display device control section 102 and the display device I/F section 103, respectively. In the display device control unit 102, VSYN
C signal clears the vertical counter 132 and continues <H
The horizontal direction counter 131 is cleared by the 3YNC signal. The LOAD signal of the display device I/F section 103 is sent to the display device control section 102, which generates a display enable signal based on this signal, switches the address selector section 104 to the address for display, and generates a data request signal;
A request is made to the storage unit 101 to transfer image data. On the other hand, the display device I/F unit 103 generates a VSYNC signal, a H5YNC signal, which is a synchronization signal of the display device, and a blank signal indicating a non-display period, and also generates image display data sent from the storage unit (here, 8 pixels) is latched into the parallel-to-serial converter 141 using a load signal (hereinafter referred to as LOAD signal), and the serialized data is sent to the display device. Here, a blank signal indicating a non-display period related to horizontal direction scanning is referred to as an HBLANK signal, and a blank signal related to the vertical direction is referred to as a VBLANK signal. FIG. 16 is a diagram showing a time chart of control signals for scanning a CRT to display image data. Furthermore, FIG. 17 shows a time chart showing in detail the control timing of one line scan at the start of display.

The outputs of the two counters (horizontal counter and vertical counter) are connected and sent to address selector section 104.
A storage address is provided to the storage unit 101 via. First, at the start of display, the address of the storage unit 101 is set to 0. At that time, when a display data request signal is sent to the bus control unit 105, a control signal is sent from the bus control unit 105 to the storage unit 101, and the upper left 8 pixels of the image data stored at address 0 are displayed as display data. Display device 1/
Sent to Fm103. At the next display data request signal ON timing, only the horizontal direction counter 131 is incremented, and the image data stored at address 1 in the storage section is
The data is sent to the display device as display data. Thereafter, image data transmission is repeated in the same manner until the HBLANK signal is turned on. Then, when the HBLANK signal turns on, the display of one line of image data is completed. Upon generation of the next H5YNC signal, in the display device control unit 102, the horizontal counter 131 is cleared, the vertical counter 132 is incremented, and image data transfer of the next row is started. The address (pit-chX], ) is sent to the storage unit 101 as an address, and the image data on the second line is output from the storage unit 101 as display data. In this way, one line of image data is sent to the display device for each H5YNC signal. When the last data of the last row is sent, the VBLANK signal turns on,
At the next VSYNC signal, scanning is started again from the upper left corner of the CRT, and this is repeated thereafter.

[Problems to be Solved by the Invention] However, in the above conventional example, the reading of one line of image data was synchronized with the timing of the H3YNC signal, so when a vertical CRT is adopted, in order to suppress flickering on the CRT screen, In order to continue scanning at the same VSYNC signal frequency as that of a horizontal CRT, it was necessary to set the HSYNC signal frequency high. However, when the H3YNC signal frequency is increased, it is necessary to read out image data from the storage section faster, and as a result, it is necessary to use a high-speed memory for the storage section. Furthermore, increasing the frequency of the H3YNC signal is
This increases the current flowing through the deflection yoke (a coil that controls the magnetic field to deflect the electrons emitted from the electron gun) in the CRT, causing problems such as heat generation and an increase in the rank of components. For this reason, the vertically elongated CRT has the drawback of being expensive.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide an image control device that can efficiently input and output image data with a simple configuration.

[Means for Solving the Problems] In order to achieve the above object, an image control device of the present invention has the following configuration. That is, the image control device stores image data and controls the input/output of the image data, and includes a storage means for storing the image data, and one address of the image data when inputting/outputting the image data. input/output data rearranging means for rearranging the image data according to the section, instruction means for instructing to change the reading direction of the image data from the storage means when displaying the image data, and following instructions from the instruction means, address generation means for generating an address of the storage means;
and a display data rearranging means for rearranging the image data read from the storage means in accordance with instructions from the instruction means when displaying the image data.

[Function] With the above configuration, the present invention rearranges and stores image data for each line when writing it to the storage section, and generates an address of the storage section when reading out the image data from the storage section. By sorting the displayed data, display data can be obtained for each column.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an image control device in which the unit of input/output data is 8 bits, which is a typical embodiment of the present invention. In Figure 1, 1 is a bus mask for the CPU, graphic controller, image processor, etc., 2 is a storage section that stores image data, and generates control signals for storage section 2 etc. from bus master addresses and control signals. 3, an input/output data sorting unit that sorts the data when accessed by the bus master 1 according to a part of the address; A display device control section 5 generates a rearrangement signal for the data and other control signals during display, and an address selector switches between an address during access by the bus master 1 and an address generated by the display device control section 5 during display. 6, a display data rearrangement unit 7 for rearranging the data read from the storage unit 2 in accordance with a rearrangement signal from the display device control unit 5 in order to send it to the display device;
, and a display device I/F unit 8 that generates control signals for the display device and interfaces with the display device.

In this embodiment, each part (#7 to #0) of the storage unit 2 of the image processing device will be explained as having 2 megabits (1 megabit = 1048576 (=2'') bits). Assuming that it is 1 bit, the input and output of each bit is stored in storage units #7 to #0 for each person's 8-power unit.
Assume that each is assigned to In such a case, the address 80 representing the storage location of the image data stored in the storage unit 2 indicates that each part (#7 to #0) of the storage unit 2 has a capacity of 2 megabits (~2” bits). Therefore, it can be expressed with a length of 21 bits.Let each bit of this address AI be Ago to Ao.

Further, the total storage capacity of the storage unit 2 in this embodiment is 2 megabits x 8 = 16 megabits, so for example, 40 megabits.
With a configuration of 96 pixels (horizontal) x 4096 lines (vertical), image data of 1 pixel and 1 bit can be handled.

Next, as shown in FIG. 2(A), 1 pixel, 1 bit, 40
If the entire image data consisting of 96 pixels (horizontal) x 4096 lines (vertical) is divided into blocks of 8 lines x 8 pixels, as shown in Figure 2 (B), addresses A,
The internal configuration of l is shown in A.

~Ao is the block address of each column, A x o ”
The block address of each row can be represented by Al t, and each line address of eight rows in each block can be represented by A, ~A, respectively. Here, in particular, A8
~Ao, A2o~AI□, A,, ~A9, respectively,
M B CA 8~0 (Memory Block
ColumnAddress: Memory block column address), MBRA 8~O (Memory Block column address)
k Row Address: Memory block row address), MLNA2~O (MemoryBlock
It will be called LiNe Address (memory block line address). When bus master 1 accesses memory 2, this MB CA n and MBRA
n is passed through the address selector section 6 to the storage section 2 as it is.
B CA n (Block Column Add
ress Ni block column address), B RA n
(Block RowAddress), MBCAn=BCAn%MB
RAn=BRAn. In addition, MLNAn is the storage unit 2
It is commonly supplied to MAn (memory address) of each part.

In such a storage section 2, when displaying an image in the vertical direction, the section marked ■ of the storage section 2 is used as shown in Figure 3, and when displaying an image in the horizontal direction, the section marked ■ is used. You can use .

First, let us consider the case where the bus master 1 inputs and outputs image data. In this embodiment, the image data handled by the bus master 1 follows M L N A n as shown in FIG.
The bit swapper 41 in the input/output data rearranging unit 4 shown in A) rearranges the data, and the data is read from and written to the storage unit. Here, it is assumed that eight pixels of display data handled by bus master I are read and written through input/output data sorting section 4 with the most significant bit being B7 and the least significant bit being O. Although various methods can be applied to the rearrangement, a rearrangement method expressed by the logical formula shown in FIG. 4(B) will be considered here. If such a rearrangement method is followed, the pit swapper 41 will be a circuit composed of eight 8->1 (selecting one from eight inputs) data selectors.

This is input 42 (in?, in6.in5.in4.
in3. in2. inl.

Data input from LnO) (b7.b6.b5.b
4. b3゜b2. bl, bO) is the sort specification 44
(S2.Sl, 5(1) TE is sorted according to the specified sorting method, 8 force 43 (out7.out6
．． out5. out4. out3. out2゜outL
, outO). At this time, the rearrangement specified by the rearrangement specification 44 (S2.SL, SO) is as follows. For convenience of explanation here, for each permutation, swapS2 SIS.

(S2 SI So each has a value of 0 or 1.

However, name it "swapooo" (meaning no sorting).

When (S2.Sl, So) = (0, 0, 0), (b
7. b6. b5. b4. b3. b2. bl, bo):
swapoo(S2.Sl, So) = (0,0,
1), (b6.b7.b4.b5.b2.b3.b
O,bl) :swapOol(S2.Sl,SO)
= (0,1,0), (b5.b4.b7.b6
．． bl, bO, b3. b2) :swapolo(S
2. When (Sl, SO) = (0, 1, 1), (b4.
b5. b6. b7. bO, bl, b2. b3) :s
wapoll(S2.Sl,SO) = (1,0,0
), (b3.b2.bl, bO, b7.b6.b5
．． b4) :swaplOO(S2.Sl, SO)
= (1,0,1), (b2.b3.b[), bl
, b6. b7. b4. b5) :5vaplO1(S
2. When SL, So) = (1, 1, 0), (bl,
bo, b3. b2. b5. b4. b7. b6) :s
wapH0(S2.SL, So) = (1,1,1)
When (bo, bl, b2.b3.b4.b5.b6.
b7) :swapHl Figure 5 shows input/output sorting section 4
FIG. 2 is a block diagram showing the configuration of FIG. The aforementioned reordering swa
Since pS2 SI So has the property of returning to its original state after being performed twice, this input/output rearrangement section 4 uses the same pit swappers 51 and 52 that follow the above-mentioned rearrangement swapS2 SI SO. In such a case, the data written by the bus master 1 is rearranged in the input/output data rearranging section 4 according to swapS2 SI SO and stored in the storage section 2, and when the bus master 1 reads the data, the input/output The data rearrangement unit 4 rearranges the data again according to swaps2 SI So and reads it out. In this way, the same data as written is read out. Therefore, the bus master 1 can access the normal memory and the memory (S2.Sl.

SO) = (0,0,0), O bit, (0,0
, 1,) is 1 bit, and ((+, 1.0) is 2 bits.
Similarly, if the 7 bits are rotated in the same way when the bits are (1, 1, 1), then a method of rotating them to the right must be used as a sorting method during output. In such a case, input
Although the method of rearranging the outputs is different, the input/output data rearranging section 4 should be designed so that the same data written in the storage section 2 as seen from the bus master 1 can be read out. Bus mask 1 reorders the image data as described above.
wapS2SI 1 block (8 pixels x 8 pixels) according to SO
FIG. 6 shows the state of internal storage in the storage unit 2 when writing (line).

Next, control for reading and displaying image data written in the storage section 2 will be explained. Figure 7 (A) and Figure 7
Figure (B) shows the configuration of the display device control section 5. This display device control section 5 operates to control a vertically elongated CRT as a display device. At this time, the display device control unit 5 controls the vertically long CRT to horizontally scan from bottom to top as shown in FIG. 8, so the vertical counter 71 becomes a town count and the HSYNC signal is It is reset every time it is turned on. Furthermore, since the display device control unit 5 controls the vertically long CRT to scan vertically from left to right,
The horizontal counter 72 counts up and reaches H
It is incremented every time the 5YNC signal turns on,
Reset by VSYNC signal. Using these counter outputs, an address for the storage section 2 and a rearrangement for the display data rearrangement section 7 are specified. in this case,
Since the control signals for the display device I/F section 8 and the bus control section 3 are the same as before, the display device I/F section 8 and the bus control section 3
can be the same as before.

Regarding the reading of image data, first one block of image data (8 pixels x 8 lines) will be explained, and then the inside of one block will be explained. Since the vertical direction counter 71 counts the vertical direction (8 pixel unit) address of the display data output, the vertical counter output (VCNT8 to O) corresponds to the block row address of one block (8 pixels x 8 lines) of image data on the display screen. specify. On the other hand, since the horizontal direction counter 72 counts the horizontal direction (in units of one line) of the display data output, a part of the horizontal counter output (
HCN72-0) specifies the block column address of one block (8 pixels x 8 lines) of image data on the display screen.

Further, the remaining horizontal counter outputs (HCN72-0) are designated as the number of columns within one block of image data. Here, 40
In order to display blocked image data of 96 pixels x 4096 lines and 1 bit per pixel on a vertical CRT, horizontal counter outputs (HCN72 to 0) and vertical counter outputs (
VCNT8~0) to display block column address (DB
CA8~0), display block row address (DBRA8~
O) and the number of columns in the display block (DLNA2 to 0) as the 9th
Define as shown in Figure (A). That is, VCNT8~0
=DBRA8~0, HCNTII~3=DBCA8~0
, HCNT2-0=DLNA2-0. Also, the 9th
Figure (B) shows DMA2-0, DMA2-0 and DLNA.
The correspondence relationship between 2 to 0 and display data is shown. As can be seen from the above description, the vertical counter is controlled by the HSYNC signal, and the horizontal counter is controlled by the VSYNC signal, so that one block of image data (8 pixels x 8 lines) is processed in the row direction. Since each column is read out in accordance with the timing of the H8YNC signal, the image data is displayed by repeatedly scanning from the bottom to the top of the CRT screen and then from left to right.

Next, consider the inside of one block of image data (8 pixels x 8 lines). As shown in FIG. 7(B), the storage unit 2
Specify the rows inside the image data block of HCNT2~
It is done with 0. The display data storage address (Display
data Memory Add-res: DMA
2 to 0) are sent to the storage unit 2 via the address selector unit 6.
is supplied as MA2-O. In FIG. 10(A), H
The relationship between CNT2-0 and MA2-O is shown. Figure 10 (A
), MA2 to MA0 are connected to each memory section (#7 to
#0) will be different. This is shown in Figure 10 (B
) is indicated by the subscript number on the upper right of each pixel of the internal state of the block shown in 91. For example, HCNT2~0=(0,0,
0), the part whose subscript number is O is read out, so the data in the first line of the input to the display data sorting section 7 is the arrangement of these parts, as shown at 92 in FIG. 10(B). It becomes. Hereinafter, )(CNT2~o= (o, o,
The same holds true for i>~(1,1,1). The rearrangement designation (S2.Sl, SO) for the display data rearrangement unit 7 of the display device control unit 5 is the inversion of each bit of HCNT2 to O, so the display data rearrangement is performed as indicated by 93 in FIG. The output of section 7 is 6 in FIG.
It looks like one block of original input image data indicated by 1 has been rotated 902 clockwise. Further, as defined above, since HCNT2-0=DLNA2-0, data addresses within the image data block can be specified by DLNA2-0. However, considering that DMA2-0 is defined as the number of columns within a block, the image data is
It will be read out after being rearranged into columns. In other words, this means that the image is read out by rotating it 90 degrees counterclockwise. Here, display data sorting section 7
Considering that the output of DLNA is rotated 90° clockwise with respect to the original input image data block, DLNA
The image data read out by specifying the number of columns by 2 to 0 will be read out as the same image data as the original.

Therefore, according to this embodiment, the image data can be read out in the column direction by rearranging the image data read out from the storage section. , image data can be efficiently displayed on a vertically elongated CRT without changing the HSYNC signal frequency.

Furthermore, according to this embodiment, image data can be input and output from the bus mask without considering image data rearrangement in the storage section.

[Other Embodiments] When the storage section 2 is configured with a dynamic RAM, the bus control section 3 generates RAS, CAS, and WE, and the output address of the address selector section 6 is divided into two: RAS and CAS. It is sufficient to supply the data to the dynamic RAM according to the time.

In this embodiment, an image control device that stores data in one pixel and one bit has been described, but the present invention is not limited to this. For example, even in the case of an image processing system that stores one pixel in multiple bits, such as a display device that expresses gradation or a display device that displays color, the present invention can be applied to each bit unit.

[Effects of the Invention] As described above, according to the present invention, image data can be input and output efficiently with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an image control device that is a typical embodiment of the present invention, FIG. B) is a diagram showing the configuration of the storage unit address, Figure 3 is a diagram showing the correspondence between the storage unit 2 and the display data size, Figure 4 (A) is a diagram showing the input, output, and control data of the pit swapper, Figure 4 (B) ) is a diagram showing the logical formula for data swapping, FIG. 5 is a configuration diagram of the input/output data sorting section 4, and FIG. 6 is human data for one block of image data. FIG. 10(B) is a diagram illustrating the relationship between the number of columns and storage address; FIG. 10(B) is a diagram illustrating rearrangement of data within j block of image data; and FIGS. 11 to 17 are diagrams illustrating conventional examples. In the figure, 1... bus mask, 2... memory section, 3...
・Bus control unit, 4...I/O data sorting unit, 5.
...Display control section, 6...Address selector section, 7.
. . . Display data rearrangement unit, 8 . . . Display device I/F unit, 41 . . . Pit swapper, 71 . Figure 8 is a diagram showing the scanning of a vertically elongated CRT, Figure 9 (A) is a diagram showing the correspondence between display data addresses and horizontal and vertical counter outputs, and Figure 9 (B) is a diagram showing display data and display data. Diagram showing address correspondence, Patent applicant: Canon Co., Ltd.::j'-22; Figure (A) Figure (B) Figure 4 (A) Figure! Figure: Horizontal up count Figure: (A) Horizontal direction 6□!

Claims (1)

[Scope of Claims] An image control device that stores image data and controls input/output of the image data, comprising: a storage unit that stores the image data; input/output data rearranging means for rearranging the image data according to part of the address of the image data; instruction means for instructing to change the read direction of the image data from the storage means when displaying the image data; and the instruction means. and display data rearranging means for rearranging image data read from the storage means when displaying the image data according to instructions from the instruction means. Characteristic image control device.