JPH0478189B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a nonvolatile semiconductor device that achieves miniaturization of elements by employing novel charge injection and discharge regions.

(Prior art) A floating gate type non-volatile semiconductor memory has an electrically insulated floating gate electrode below the control gate electrode, and charges are induced in the floating gate electrode to be used as stored information. It is designed to be retained. In such a floating gate type non-volatile semiconductor memory, when writing or erasing information, a high voltage of about 20V is applied to the control gate electrode, so that a charge is transferred to the floating gate electrode through the gate oxide film. or discharge charges from the floating gate electrode. Therefore, the durability against writing and erasing information depends on the physical characteristics of the gate oxide film formed around the floating gate electrode relative to the electric field.

The structure of a conventional typical memory cell of such a floating gate type non-volatile semiconductor memory (hereinafter referred to as EEPROM) is shown in Figures 2 to 4.
Each is shown in the cross-sectional view of the figure. The cell shown in FIG. 2 is of the Intel type, and 51 is a p-type silicon substrate. A field oxide film 52 is formed on this substrate 51 to separate element regions into islands. Further, a gate oxide film 53 is formed on the surface of the element region of the substrate 51, and this element region has source and drain regions 5 in which n-type impurities are diffused.
4 and 55 are formed electrically isolated from each other. Here, the drain region 55 is the source region 5
The gate oxide film 53 has a larger area than the gate oxide film 4, and a portion of the gate oxide film 53 near the field oxide film 52 on the drain region 55 side is thinned to form a thin film portion 56. In addition, the gate oxide film 5
A floating gate electrode 57 is formed on the channel region between the source and drain regions 54 and 55 to a part of the field oxide film 52 on the side of the drain region 55, and an oxide film 58 is formed on the floating gate electrode 57. control gate electrode 5 through
9 is formed. The side surfaces of the floating gate electrode 57 and the side surfaces and top surface of the control gate electrode 59 are covered with an oxide film 60.

The EEPROM cell having such a configuration includes a thin film portion 56 between the drain region 55 and the floating gate electrode 57 for injecting electrons into the floating gate electrode 57 and emitting electrons from the floating gate electrode 57. The feature is that the voltage of the drain region 55 is set to 0V (earth voltage), and the control gate voltage is set to 0V (earth voltage).
By setting V _G to a high voltage of approximately +20V to +30V, electrons are injected from the drain region 55 through the thin film portion 56 into the floating gate electrode 57 . Also, control gate voltage V _G is 0V
and set the drain voltage V _D to +20V or +30V.
By setting the voltage to a level as high as
Electrons are emitted from floating gate electrode 57 to drain region 55 via. By injecting and emitting electrons through the thin film portion 56 in this manner, the threshold voltage Vth in the channel region is shifted, and a nonvolatile information storage function is obtained.

The cell shown in FIG. 3 is of the Motorola type, and numeral 51 is a p-type silicon substrate similar to the cell shown in FIG. is formed. A gate oxide film 53 is formed on the surface of the element region, and source and drain regions 54 and 55 are formed in this element region by diffusion of n-type impurities. Then, the thickness of the gate oxide film 53 is reduced in a region extending from the channel region to part of the source and drain regions 54 and 55, thereby forming a thin film portion 56, and a floating gate electrode 57 is formed on this thin film portion 56. It is formed. Furthermore, a control gate electrode 59 is formed on the floating gate electrode 57 with an oxide film 58 interposed therebetween. Also, the side surfaces of these floating gate electrodes 57 and the control gate electrodes 5
The side and top surfaces of 9 are covered with an oxide film 60.

The feature of the EEPROM cell having such a structure is that the channel region and the source and drain regions 54, 5
A thin film portion 56 of a gate oxide film 53 made of a silicon oxide film is formed on a part of the floating gate electrode 57, and the injection of electrons into the floating gate electrode 57 and the emission of electrons from the floating gate electrode 57 are performed as shown in FIG. The floating gate electrode 57 and the drain region 55 are
The thin film portion 5
6.

The cell shown in FIG. 4 is of the National Semiconductor type, and its basic cross-sectional structure is almost the same as that shown in FIG. 55 has been extended. A gate oxide film 5 is formed on a part of this extended drain region 55.
A thin film portion 56 of No. 3 is formed, and electrons are injected into and emitted from the floating gate electrode 57 through this thin film portion 56.

Incidentally, since all of the conventional EEPROMs described above inject and emit electrons through tunneling, the thickness of the thin film portion 56 needs to be as thin as, for example, about 100 Å in order to inject and emit electrons efficiently. . Further, when writing or erasing information, a high electric field is applied to the thin oxide film using the capacitive coupling ratio between the control gate electrode and the floating gate electrode and between the floating gate electrode and the substrate. Since floating gate electrodes and control gate electrodes are usually made of polycrystalline silicon, it is difficult to form a highly reliable thin oxide film on this polycrystalline silicon layer. Therefore, in order to make the capacitive coupling ratio as described above appropriate, it is necessary to increase the overlapping area of the control gate electrode and the floating gate electrode to increase the capacitive coupling. For this,
Conventionally, the disadvantage is that the cell area becomes large, making it difficult to increase the capacity.

(Problems to be Solved by the Invention) As described above, conventional nonvolatile semiconductor devices have the disadvantage that the cell area becomes large and it is difficult to increase the capacity.

This invention was made in consideration of the above circumstances, and its purpose is to reduce the cell area, increase cell density, and reduce the voltage required when writing and erasing information. It is an object of the present invention to provide a method for manufacturing a nonvolatile semiconductor device that can be manufactured in a number of ways.

[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a nonvolatile semiconductor device of the present invention includes:
forming an element isolation insulating film on the surface of a first conductivity type silicon semiconductor substrate and forming an island-shaped element region separated by the insulating film; and forming a first gate insulating film on the element region. forming an opening, selectively removing a part of the first gate insulating film to form an opening, and applying impurities of a second conductivity type so as to cover the surface of the base exposed from the opening. a step of selectively forming a first polycrystalline silicon layer including a second gate insulating film on the surface of the first polycrystalline silicon layer by a thermal oxidation method; a step of diffusing a second conductivity type impurity contained in the substrate surface to form a second conductivity type first drain region; forming a floating gate electrode by selectively continuously forming a second polycrystalline silicon layer on the substrate; forming a second drain region to be connected to the first drain region by diffusing impurities of a second conductivity type on the surface and forming a source region; and a third step on the surface of the floating gate electrode. The method includes a step of forming a gate insulating film, and a step of depositing a third polycrystalline silicon layer on the third gate insulating film to form a control gate electrode.

(Function) In the nonvolatile semiconductor device of the present invention, a polycrystalline silicon layer is selectively formed on the exposed surface of a silicon semiconductor substrate, and an oxide film is further formed on this polycrystalline silicon layer. The oxide film thus formed has a critical electric field that causes injection and emission of tunnel electrons about half as low as that of an oxide film formed on a silicon semiconductor substrate. Therefore, electrons can be efficiently injected and emitted even if the film is relatively thick.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing each step of the method for manufacturing a nonvolatile semiconductor device according to the present invention, and only one memory cell is shown. Hereinafter, the manufacturing process will be sequentially explained with reference to the drawings.

First, an oxide film 12 is grown to a thickness of about 1000 Å on a p-type silicon semiconductor substrate 11 by thermal oxidation. Next, a silicon nitride film (Si ₃ N ₄ film; silicon nitride film) 13 is formed on this oxide film 12.
It is deposited to a thickness of about 3000 Å. Furthermore, a photoresist film (not shown) is deposited on this silicon nitride film 13, and this photoresist film is patterned to form an etching mask with openings at the positions where field oxide films are to be formed to separate device regions into islands. form. Next, using this mask, the silicon nitride film 13 is selectively etched to open the area where the field oxide film is to be formed. Next, after removing the photoresist mask, the silicon nitride film 13 patterned in advance is removed.
To form a channel stopper, boron B ions were accelerated at a voltage of 40 KeV and at a dose of 5× using
Ion implantation is performed under conditions of 10 ¹³ /cm ² to selectively form ion implantation regions 14 on the surface of the substrate 11 (first
Figure a).

Next, with the silicon nitride film 13 remaining,
Perform wet oxidation at 1000℃ using H ₂ O,
An oxide film is grown on the exposed surface of the substrate 11 to form a field oxide film 15. At this time, the boron atoms in the ion implantation region 14 are activated, and a p ⁺ type inversion prevention layer 16 is simultaneously formed under the field oxide film 15 (as shown in FIG. 1B).

Next, dry etching is performed to remove the silicon nitride film 13, and then the oxide film 12 is etched away using an ammonium fluoride solution (as shown in FIG. 1c).

Next, a gate oxide film 17 of about 500 Å is grown on the surface of the substrate 11 by a thermal oxidation method, and then a photoresist is applied to the entire surface, and a silicon oxide thin film for writing and erasing in the element area is planned to be formed using a photolithography method. is formed in a resist pattern 18 having an opening. Next, using this pattern 18 as a mask, the gate oxide film 1 is removed using an ammonium fluoride solution.
7 is selectively etched to remove the gate oxide film 1.
An opening 19 is formed in 7 (as shown in FIG. 1d).

Next, after removing the resist pattern 18,
A polycrystalline silicon layer 20 is grown over the entire surface. At this time, this polycrystalline silicon layer 20 contains arsenic (As).
Ion implantation is performed to approximately 5×10 ¹⁵ /cm ² . continue,
A resist pattern (not shown) having a shape that covers the opening 19 is formed on the polycrystalline silicon layer 20, and the polycrystalline silicon layer 20 is selectively etched using this resist pattern as a mask. After removing this resist pattern,
An oxide film 21 with a thickness of about 300 Å is formed on the surface of the remaining polycrystalline silicon layer 20 by thermal oxidation. At this time, arsenic ions previously contained in the polycrystalline silicon layer 20 are diffused into the surface of the substrate 11, and an n ⁺ type diffusion layer 22 is simultaneously formed (as shown in FIG. 1e). In this step, an oxide film 21 is formed on the surface of the polycrystalline silicon layer 20.
However, it becomes an insulating film through which electrons pass when injecting and emitting electrons to and from the floating gate electrode that will be formed later.

Next, a polycrystalline silicon layer is grown over the entire surface. At this time, predetermined impurity ions are also implanted into this polycrystalline silicon layer. Subsequently, a resist pattern (not shown) is formed on this polycrystalline silicon layer. Then, using this resist pattern as a mask, the polycrystalline silicon layer is selectively etched to form a floating gate electrode 23. In this step, although not shown, in addition to the memory cells, gate electrodes and wiring of MOS transistors for necessary peripheral circuits are patterned at the same time (as shown in FIG. 1f).

Next, using the floating gate electrode 23 and the field oxide film 15 as masks, arsenic ions (As) are applied at an acceleration voltage of 40 KeV and a dose of 5×.
Ion implantation was performed under the condition of 10 ¹⁵ /cm ² , and then the substrate 11
The implanted arsenic ions are activated to form n ⁺ type source region 24 and drain region 24. At this time, the drain region 25 is formed in advance.
It is electrically connected to the n ⁺ type diffusion layer 22, and the substantial drain region is the drain region 25.
It consists of an n ⁺ type diffusion layer 22 (illustrated in FIG. 1g).

Next, thermal oxidation is performed for 30 minutes in an O ₂ atmosphere at 900°C to form an 800%
A gate oxide film 26 for a control gate electrode is formed to a thickness of Å (as shown in FIG. 1h).

After this, a polycrystalline silicon layer is grown to a thickness of 4000 Å over the entire surface. Next, heat treatment was performed for 30 minutes in a POCl ₃ atmosphere at 900°C to perform n-type diffusion into this polycrystalline silicon layer, and then a resist pattern (not shown) was formed on top of the polycrystalline silicon layer to mask the area where the control gate electrode was to be formed. is formed, and using this as a mask, the polycrystalline silicon layer is selectively etched to form a control gate electrode 27 (as shown in FIG. 1i).

Thereafter, an interlayer insulating film 28 such as PSG (phosphorus silicon glass) is deposited in accordance with the normal manufacturing process for MOS type integrated circuits, and contacts are made to the interlayer insulating film 28 to the surfaces of the source region 24 and drain region 25. Holes 29 and 30 are opened, and then a metal wiring material, such as aluminum, is deposited by vacuum evaporation and patterned to form a source electrode 31 and a drain electrode 32. Furthermore, after this, a passivation film 3 is applied to the surface.
3 is deposited to complete the EEPROM (as shown in FIG. 1J).

Here, the n ⁺ type diffusion layer 22 is formed to be electrically connected to the drain region 25, and
The n ⁺ -type diffusion layer 22 is formed in a channel region between the drain region 25 and the source region 24 .
Additionally, a polycrystalline silicon layer 20 is formed over this channel region.

The initial threshold voltage Vth of a cell having such a configuration is determined by the threshold voltage of the channel region under the gate oxide film 17. The n ⁺ -type diffusion layer 22 in the channel region is formed by implanting arsenic ions, but it may also be formed by implanting phosphorus ions, or by implanting arsenic and phosphorus or this and boron. It may also be formed by implanting ions.

As described above, the method of this embodiment is characterized in that the thin oxide film 21 is formed on the polycrystalline silicon layer 20 by thermal oxidation, and the floating gate electrode 23 is formed on this. When the thin oxide film 21 made of silicon oxide formed in this way is used, the oxide film 21 on the polycrystalline silicon layer 20
The apparent barrier height is about half that of a conventional oxide film formed on a silicon substrate. That is, polycrystalline silicon layer 2
The oxide film 21 formed on the substrate has a critical electric field that causes injection and emission of electrons due to tunnel current to be about half lower than that of the oxide film formed on the substrate. Therefore, it is not necessary to make the oxide film 21 extremely thin (for example, 100 Å as in the conventional case).
When the thickness is around 300Å, the cell area is approximately 1/2 that of the conventional one.
It becomes below. In addition, the control gate electrode 27
If the overlapping area between the floating gate electrode 23 and the floating gate electrode 23 is set to the same level as the conventional one, the voltage for writing and erasing information can be reduced to about two-thirds or less of the conventional one. Therefore, according to the memory device of the above embodiment, the oxide film 21 on the polycrystalline silicon layer 20
By appropriately setting the film thickness, the cell area can be reduced and the write and erase voltages can be reduced, making it possible to realize a highly integrated and highly reliable EEPROM.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made. For example, in the above embodiment, the case where the floating gate electrode 23 is made of a polycrystalline silicon layer has been explained, but this is not possible with a high melting point metal silicide layer made of a high melting point metal such as molybdenum or titanium and silicon, or a polycrystalline silicon layer and a high melting point metal silicide layer of silicon. It may also be configured by a laminated film with a melting point metal silicide layer.

[Effects of the Invention] As explained above, according to the present invention, it is possible to reduce the cell area and increase the density of the cell, and to reduce the voltage required when writing and erasing information. It is possible to provide a method for manufacturing a nonvolatile semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining an embodiment of the present invention, and FIGS. 2 to 4 are sectional views of conventional devices. 11... p-type silicon semiconductor substrate, 12...
Oxide film, 13... Silicon nitride film, 14... Ion implantation region, 15... Field oxide film, 16...
... p ⁺ type inversion prevention layer, 17 ... gate oxide film,
18...Resist pattern, 19...Opening, 2
0... Polycrystalline silicon layer, 21... Oxide film, 22
... n ⁺ type diffusion layer, 23 ... floating gate electrode, 24 ... source region, 25 ... drain region, 26 ... gate oxide film for control gate electrode, 27 ... control gate electrode, 28
...Interlayer insulating film, 29, 30... Contact hole, 31... Source electrode, 32... Drain electrode, 33... Passivation film.

Claims (1)

[Claims] 1. A step of forming an insulating film for element isolation on the surface of a silicon semiconductor substrate of a first conductivity type and forming an island-shaped element region separated by the insulating film; forming a first gate insulating film; selectively removing a portion of the first gate insulating film to form an opening; selectively forming a first polycrystalline silicon layer containing impurities of a second conductivity type; forming a second gate insulating film on the surface of the first polycrystalline silicon layer by thermal oxidation; forming a first drain region of a second conductivity type by diffusing impurities of a second conductivity type contained in the first polycrystalline silicon layer onto the surface of the substrate; a step of selectively forming a second polycrystalline silicon layer continuously on a part of the first gate insulating film to form a floating gate electrode; a step of diffusing impurities of a second conductivity type into the surface of the substrate using a mask to form a second drain region and a source region so as to be connected to the first drain region; The method includes the steps of forming a third gate insulating film on the surface of the gate electrode, and depositing a third polycrystalline silicon layer on the third gate insulating film to form a control gate electrode. A method for manufacturing a non-volatile semiconductor device.