JPH047835A - Manufacturing method of wiring components - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to wiring members, particularly barrier metal wiring,
The present invention relates to a technique that is effective when applied to a wiring member having a layered wiring structure in which aluminum wirings are sequentially laminated.

[Conventional technology]

Although the DRAM being developed by the present inventor is not a known technology,
For example, as described in Japanese Patent Application No. 1-65848, a layered wiring structure is used. The DRAM under development has a two-layer wiring structure, and a laminated structure is applied to each of the first-layer wiring and the second-layer wiring. Specifically, the stacked structure is applied to each of the data line (first layer wiring) and word line (second layer wiring, shunt word line) connected to the memory cell of the DRAM.

The wiring having the laminated structure has a three-layer structure in which a Mo5iz film, an aluminum alloy film, and a MoS xz film are sequentially laminated. The aluminum alloy film in the middle of the laminated structure is a substantial wiring portion, has a low specific resistance value, and is configured for the purpose of increasing signal transmission speed. the lower MoSi film, the aluminum atoms of the intermediate aluminum alloy film;
Semiconductor elements such as MO8FET for cell selection of memory cells
The purpose of this structure is to prevent mutual diffusion of silicon atoms in the diffusion layer (semiconductor region). That is, the underlying MoSi
.

The film is used as a barrier metal film. Upper Mo S
The i2 film is constructed for the purpose of preventing aluminum hillocks growing from the surface of the intermediate aluminum alloy film.

A passivation film for insulation isolation is formed between each of the first layer wiring and the second layer wiring of the DRAM.

This passivation film is mainly composed of, for example, a silicon oxide film. A final passivation y is formed in the upper layer of the second layer wiring on the uppermost layer. DRAM is usually sealed in a resin mold type package, and its moisture resistance is somewhat low.

The final passivation film is mainly composed of a silicon nitride film with high moisture resistance.

In this way, the DRAM can prevent interdiffusion of atoms and hillocks as described above by using wiring in a stacked structure, thereby reducing wiring defects and achieving high reliability.

[Problem to be solved by the invention]

However, the inventor found the following problems.

In the wiring of the above-mentioned laminated structure, especially the second layer wiring, the stress of the silicon nitride film is greater than that of the silicon oxide film, so the stress applied by the final passivation film is large.

As a result, stress migration occurs in the aluminum alloy film, resulting in frequent disconnection defects in the wiring in the stacked structure. This stress migration occurs significantly when the wiring width becomes smaller than the aluminum grain size due to higher integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can reduce disconnection defects in wiring in a laminated structure in a wiring member having wiring in a laminated structure.

Another object of the present invention is to provide a manufacturing method that can achieve the above object.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

A layered wiring structure in which barrier metal wiring and aluminum wiring are laminated on a base insulating film is extended.

In the wiring member that covers the wiring in the laminated structure with a passivation film, a cutout portion is provided in the aluminum wiring of the wiring in the laminated structure to cross in the width direction of the wiring. This defective portion is formed in the shape of a notch or a slit. Further, the defective portion is provided in a wiring having a laminated structure and having a wiring width smaller than the aluminum grain size of the aluminum wiring.

[For production]

According to the above-mentioned means, the passivation film absorbs the stress applied to the aluminum wiring of the layered wiring in the defect portion provided in the aluminum wiring, and the stress applied to the aluminum wiring can be reduced, so that the stress on the aluminum wiring can be reduced. It is possible to reduce the occurrence of migration and prevent disconnection defects in wiring in a laminated structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having wiring in a stacked structure.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) The structure of a semiconductor integrated circuit device having wiring in a layered structure according to Example I of the present invention is shown in FIG. 1 (a sectional view of main parts) and FIG. 2 (a top view of the main part).

As shown in FIG. 1, a semiconductor integrated circuit device is composed of a semiconductor substrate 1 made of single crystal silicon. Although the semiconductor integrated circuit device is not limited to this, for example, it is configured with a DRAM.

A semiconductor element, for example, MI5, is provided on the main surface of the semiconductor substrate l.
A diffusion layer (semiconductor region) 2 is formed to form each of the source region and drain Mj44 of the FET.

Basically, the diffusion layer 2 is of a conductivity type opposite to that of the semiconductor substrate 1. In a DRAM, the MISFET is a memory cell selection MISFET of a memory cell, and a MISFET forming a peripheral circuit.

A part of the wiring 5 having a laminated structure is connected to the diffusion layer 2 . The wiring 5 having a laminated structure extends over the passivation film (underlying insulating film) 3 and is electrically connected through the connection hole 4 formed in the passivation film 3 . The passivation film 3 is formed mainly of a silicon oxide film, for example.

The wiring 5 having the laminated structure has a three-layer wiring structure in which MoSi, film 5A, aluminum alloy film 5B, MoSi, and film 5C are sequentially laminated. Lower layer MoSi, film 5A
are the silicon atoms of the diffusion layer 2 and the aluminum alloy film 5B.
It is used as a barrier metal film to reduce the interdiffusion of aluminum atoms and prevent the alloy spike phenomenon. This lower layer M o S 1. , membrane 5A is 40-6
It is formed with a film thickness of about 0 [nml]. The intermediate layer aluminum alloy film 5B is the main part of the wiring 5 having a laminated structure, and is configured for the purpose of increasing the signal transmission speed. The intermediate layer aluminum alloy film 5B is made of Cu, Si, or aluminum to which Cu and Si are added. Cu has the effect of improving electromigration breakdown voltage. Si is added to the intermediate layer aluminum alloy film 5B in the diffusion layer 2.
This has the effect of reducing the diffusion of silicon atoms from the alloy and improving the alloy spike breakdown voltage. In addition, the wiring 5 of the laminated structure
The intermediate layer may be composed of an aluminum film to which the above-mentioned additives are not added. Intermediate layer aluminum alloy film 5B
For example, the film thickness is about 500 to 1200 [nml]. The upper layer MoSi2 film 5C is configured for the purpose of reducing aluminum hillocks generated on the surface of the intermediate layer aluminum alloy film 5B. Upper layer MoSi, 95G is 1
It is formed with a film thickness of about 5-40 [nml]. However, the film thicknesses of the lower layer MoSi film 5A and the upper layer Mo5iz film 5C need to be thick enough not to melt when a current flows through the defective part 6 of the aluminum alloy film 5B in the present invention.
It changes depending on the current density used.

The wiring 5 having the laminated structure constructed in this way has an intermediate layer of aluminum alloy film 5B arranged at a predetermined pitch in its extending direction.
A cutout portion 6 is provided across the wiring width direction. 1st
As shown in the figure and FIG. 2, the defective portion 6 is formed in the shape of a slit that completely crosses the wiring 5 of the laminated structure in the wiring width direction. The defective portion 6 is formed by dividing the intermediate layer aluminum alloy film 5B of the wiring 5 in the laminated structure into a plurality of parts in its extending direction.
A space is formed in between.

The defective portion 6 is basically formed in the aluminum alloy film 5B of the wiring 5 having a laminated structure in which the wiring width dimension is smaller than the aluminum grain size (for example, the defective portion 6).
is approximately 2 [μm] when the aluminum particle size is approximately 2 [μm].
The wiring 5 is formed in a laminated structure having a wiring width dimension of about 1 [μm] or less, which is less than one-fold. The wiring 5 having a laminated structure having this kind of wiring width dimension is basically used as a signal wiring. The power supply wiring has a larger width than the above-mentioned wiring width for the purpose of ensuring electromigration withstand voltage. Therefore, the defective portion 6 is formed at least in the wiring 5 having a laminated structure used as a signal wiring.

A final passivation film 7 is formed on the wiring 5 having the laminated structure. Final passivation film 7
is mainly composed of a silicon nitride film deposited by plasma CVD, which has higher moisture resistance than a silicon oxide film, for the purpose of improving moisture resistance.

Note that this example is provided for the purpose of simplifying the explanation.

This is a case where the present invention is applied to a semiconductor integrated circuit device having a single layer wiring structure, which is a single layer of the wiring 5 having a laminated structure. It can also be applied to a semiconductor integrated circuit device having.

Next, regarding the method for manufacturing the above-mentioned semiconductor integrated circuit device,
A brief explanation will be given using FIGS. 3 and 4 (cross-sectional views of the main parts shown in each manufacturing process) and FIG. 5 (a plan view of the main parts in the process shown in FIG. 4).

First, a diffusion layer 2 is formed on the main surface of the semiconductor substrate 1, and a passivation film 3 is formed over the entire main surface of the semiconductor substrate 1, including the top of the diffusion layer 2. Thereafter, a connection hole 4 is formed in the passivation film 3 above the diffusion layer 2, and the surface of the diffusion layer 2 is exposed from the connection hole 4.

Next, as shown in FIG. 3, a layered interconnect 5 connected to the surface of the diffusion layer 2 through the connection hole 4 is formed on the passivation film 3. The wiring 5 having a laminated structure is made of MoSi
, film 5A, aluminum alloy film 5B, MoSi, film 5C
are formed by sequentially depositing each of them and patterning them.

MoSi, films 5A and 5C, and aluminum alloy film 5B are each deposited by, for example, a sputtering method. MoSi.

Patterning of each of the films 5A, 5C and the aluminum alloy film 5B is performed by dry etching using an etching mask formed by well-known photolithography. For example, a CQ-based etching gas is used for dry etching.

Next, an etching mask 10 is formed using photolithography over the entire surface including the wiring 5 of the laminated structure. This etching mask 10 is.

Slit-shaped openings 10A are provided which are arranged at a predetermined pitch in the extending direction of the wiring 5 having a laminated structure and which cross the wiring width direction of the wiring 5 having a laminated structure. This opening 10A is formed in a size larger in the same direction than the wiring width dimension of the wiring 5 of the laminated structure in order to expose both opposing sides of the intermediate layer aluminum alloy film 5C.

Next, as shown in FIGS. 4 and 5, using the etching mask 10, the aluminum alloy film 5B of the intermediate layer of the wiring 5 of the laminated structure exposed from the opening 10A is selectively etched to remove the defective part. form 6. Etching of the aluminum alloy film 5B is performed, for example, by wet etching using a mixed acid aluminum etching solution.

Thereafter, the etching mask 10 is removed, and a final passivation film is formed over the entire surface including the wiring 5 of the laminated structure.

In this way, the MoSi2 film (barrier metal wiring) 5A is formed on the passivation film (base insulating film) 3.

A wiring 5 having a laminated structure in which an aluminum alloy film 5B and a MoSi2 film 5C are sequentially laminated is extended, and the wiring 5 having a laminated structure is
In a semiconductor integrated circuit device in which the wiring 5 is covered with a final passivation film 7, a cutout 6 is provided in the aluminum alloy film 5B of the wiring 5 having the laminated structure so as to cross the wiring width direction.

This defective portion 6 has a slit shape. Further, the defective portion 6 is provided at least in the wiring 5 of the laminated structure whose wiring width is smaller than the aluminum grain size (for example, the power supply wiring may or may not be provided). The final passivation film 7 absorbs the stress applied to the intermediate layer aluminum alloy film 5B of the wiring 5 in the laminated structure in the space of the defective part 6, and can reduce the stress applied to the aluminum alloy film 5B. It is possible to reduce the occurrence of stress migration in the wiring 5B and prevent disconnection defects in the wiring 5 having a laminated structure.

When stress migration occurs in the intermediate layer aluminum alloy film 5B of the interconnect 5 having a stacked structure, it becomes unclear where and how much resistance is added. Furthermore, when stress migration occurs in the intermediate layer aluminum alloy film 5B of the wiring 5 in the laminated structure, the aluminum alloy film 5B is disconnected and the upper and lower M o S 1! There is a high possibility that membranes 5C and 5A will be destroyed. However, in the present invention, the defect portion 6 having a predetermined resistance value is added at a predetermined position to the wiring 5 of the laminated structure in advance, so the above-mentioned problem does not occur. The Mo5iz film 5A in the lower layer of the wiring 5 in this laminated structure is used as a barrier metal film, and the MoSi21115G in the upper layer is used as a hillock prevention film, and is also actively used as a wiring material.

Further, the present invention provides an aluminum alloy film 5B and a MoSi2 film 5A formed under the aluminum alloy film 5B, or a MoSi2 film 5A formed on the upper layer.
The present invention may be applied to the wiring 5 having a two-layer stacked structure made of the O812 film 5C.

Further, the present invention provides a structure in which the lower layer or the upper layer of the wiring 5 of the laminated structure is formed of a TiSi2 film, TaSi, film-WSi, film, TiW.
It may be formed of any film or the like.

(Example ■) This example (■) is the second actual flow side of the present invention, in which a cutout portion that crosses a part of the wiring in the wiring width direction of the laminated structure is provided.

The configuration of a semiconductor integrated circuit device having wiring in a layered structure, which is Embodiment (2) of the present invention, is shown in FIG. 6 (a sectional view of the main part) and FIG. 7 (a plan view of the main part).

In the semiconductor integrated circuit device of Example H, as shown in FIGS. 6 and 7, a defect portion 6 is formed that crosses a portion of the wiring 5 in the layered structure in the wiring width direction.

This defective portion 6 has a notch shape.

The defective portion 6 can be formed by wet etching in the same manner as in the manufacturing method of Example I using an etching mask having an opening indicated by the reference numeral 10A in FIG. 7 and surrounded by a two-dot chain line. .

The opening 10A of the etching mask is formed by exposing the - (left side) side surface of the intermediate layer aluminum alloy film 5B of the wiring 5 having a laminated structure.

As described above, according to the semiconductor integrated circuit device of the present embodiment (2), substantially the same effects as those of the above-mentioned embodiment I can be achieved, and the aluminum alloy film 5 of the wiring 5 of the laminated structure can be
Since the aluminum alloy film 5B can remain in the defective portion 6 of B, the resistance value of the wiring 5 having a laminated structure can be reduced.

Although the invention made by the present inventor has been specifically explained above based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention is not limited to semiconductor integrated circuit devices that have wiring in a laminated structure, but can be applied to printed wiring boards, etc. that have a laminated structure. A brief explanation of the effects obtained is as follows.

In a wiring member having a layered structure of wiring, disconnection defects in the layered structure of the wiring can be reduced.

[Brief explanation of drawings]

Figure 1 is an example of the present invention! FIG. 2 is a cross-sectional view of a main part of a semiconductor integrated circuit device having interconnects with a laminated structure, and FIG. 2 is a plan view of a main part of the semiconductor integrated circuit device. 3 and 4 are cross-sectional views of the main parts shown in each manufacturing process for explaining the manufacturing method of the semiconductor integrated circuit device, and FIG. 5 is a plan view of the main parts in the process shown in FIG. 4. FIG. 6 is a cross-sectional view of a main part of a semiconductor integrated circuit device having wiring in a stacked structure according to an embodiment (2) of the present invention, and FIG. 7 is a plan view of a main part of the semiconductor integrated circuit device. In the figure, 3... Passivation film, 5... Laminated structure wiring, 5A, 5C-MoSi, film, 5B... Aluminum alloy film, 6... Defect part, 7... Final passivation film, 10... Etching mask, IO
A... It is an opening. Figure 1 Figure 2

Claims (1)

[Scope of Claims] 1. A wiring member having a layered structure in which barrier metal wires and aluminum wires are laminated on a base insulating film, and in which the layered wires are covered with a passivation film. A wiring member, characterized in that the aluminum wiring of the wiring is provided with a defective portion extending across the wiring width direction. 2. The wiring member according to claim 1, wherein the defective portion is formed in a notch shape or a slit shape. 3. The wiring member according to claim 1 or 2, wherein the defective portion is provided in a wiring having a laminated structure in which the wiring width dimension is smaller than the aluminum grain size of the aluminum wiring.