JPH0478960A - Logical simulator unit time setting system - Google Patents

Abstract

PURPOSE:To obtain various utilizing methods in accordance with the degree of skill by allowing the system to have a function for determining automatically an optimal unit time from a delay used for a simulation and the minimum resolution time of an input pattern. CONSTITUTION:The system is provided with a unit time input means 1 for receiving a unit time designating instruction (a) and outputting an instruction value as a unit time candidate (b), and a delay minimum resolution time determining means 2 for outputting the minimum resolution time being the greatest common measure of a delay time from delay definition data (f) as a unit time candidate (c). Also, this system is provided with an input pattern minimum resolution time determining means 3 for outputting the minimum resolution time being the greatest common measure a time interval until a data value of input pattern data (g) is varied as a unit time candidate (d), and a unit time determining means 4 for determining its value, and the greatest common measures of the unit time candidate (c) and (d), when an output of the unit time candidate (b) exists, and when the unit time candidate (b) does not exist, respectively. In such a way, various utilizing methods can be obtained in accordance with the degree of skill of a user.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulator unit time setting method, particularly to a logic simulator unit time setting method applied to an event-driven logic simulator.

[Conventional technology]

Conventionally, this type of logic simulator unit time setting method is
It has a unit time input means which, upon receiving a unit time designation instruction from a user, replaces the specified unit time value with the specified time. That is, until a specified value is input by the user as a unit time designation instruction, the unit time close input means outputs the predefined value of the unit time as the unit time, and outputs the specified value as the unit time designation instruction. When input, the indicated value is output as a unit time.

[Problem to be solved by the invention]

The conventional logic simulator unit time setting method described above is
Since the time specified by the default value or the time specified by the user is used as the unit time, if the unit time is too small, there will be many times when no events occur, increasing the wasted time to advance the simulation time, and slowing down the simulation speed. However, if the unit time is too large, the simulation accuracy may become poor or unnecessary alarms may be detected.

[Means to solve the problem]

The logic simulator unit time setting method of the present invention includes a unit time input means for receiving a unit time designation instruction from a user and outputting an instruction value as a unit time candidate 1, and delay definitions of elements constituting a circuit for logic simulation. Delay minimum resolution time determining means for outputting a minimum resolution time that is the greatest common divisor of delay times from the data as a unit time candidate 2;
Minimum input pattern that outputs the minimum resolution time, which is the greatest common divisor of the time interval until the data value of the input pattern data defined by the signal wave input from the outside to the circuit for logic simulation, changes as unit time candidate 3. resolution time determining means; and unit time determining means for determining the value of the unit time candidate 1 when there is an output, and determining the greatest common divisor of the unit time candidates 2 and 3 as the unit time when there is no unit time candidate 1. Constructed by including.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The embodiment shown in FIG. 1 includes a unit time input means 1 which receives a unit time designation instruction a from a user and outputs a unit time candidate, and a unit time candidate C which determines the minimum resolution time from delay definition data f. delay minimum resolution time determining means 2 for outputting delay minimum resolution time, input cover turn minimum resolution time determining means 3 for determining the minimum resolution time from input cover turn data g and outputting unit time candidate d; and a unit time determining means 4 for determining a unit time e of the logic simulator from d.

The unit time input means 1 outputs an instruction value as a unit time candidate only when the unit time designation instruction a is input by the user. The minimum delay resolution time determining means 2 outputs the minimum resolution time, which is the least common divisor of delay times, as a unit time candidate C from delay definition data f that defines the delay times of elements constituting the circuit to be simulated. . The input cover turn minimum resolution time determining means 3 determines the minimum resolution time which is the greatest common divisor of the time interval until the data value of the input cover turn data g, which is defined by the signal waveform input from the outside to the circuit undergoing logic simulation, changes. Output as unit time candidate d. When a unit time candidate is inputted, the unit time determination means 4 is used when the user inputs a unit time designation instruction a.
If , the indicated value is used as the unit time. If unit time designation instruction a is not input, unit time e is output with the greatest common divisor of unit waiting candidates C and d as the unit time.

〔Effect of the invention〕

As explained above, the logic simulator unit time setting method of the present invention can speed up the simulation by having the function of automatically determining the optimal unit time from the delay used in the simulation and the minimum resolution time of the input pattern. At the same time, it is also possible to perform simulations with intentionally low precision using the conventional unit time instruction function by users, which has the effect of providing a variety of usage methods depending on the user's skill level when performing logical simulations. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Unit time input means, 2... Delay minimum resolution time determination means, 3... Input cover turn minimum resolution time determination means, 4... Unit time determination means.

Claims (1)

[Claims] unit time input means that receives a unit time designation instruction from the user and outputs the specified value as unit time candidate 1; and a minimum input unit that is the greatest common divisor of delay times from delay definition data of elements constituting the circuit for logic simulation. Delay minimum resolution time determining means that outputs resolution time as unit time candidate 2, and the maximum time interval until the data value of input pattern data defined by the signal wave input from the outside to the circuit for logic simulation changes. An input pattern minimum resolution time determining means that outputs the minimum resolution time which is a common divisor as a unit time candidate 3; and when there is an output of the unit time candidate 1, its value is output, and when there is no unit time candidate 1, the unit time candidate 1. A logic simulator unit time setting method, comprising: unit time determining means for determining the greatest common divisor of 2 and 3 as a unit time.