JPH0479352A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0479352A
JPH0479352A JP2195197A JP19519790A JPH0479352A JP H0479352 A JPH0479352 A JP H0479352A JP 2195197 A JP2195197 A JP 2195197A JP 19519790 A JP19519790 A JP 19519790A JP H0479352 A JPH0479352 A JP H0479352A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
semiconductor device
cap
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2195197A
Other languages
Japanese (ja)
Inventor
Koji Minami
浩司 南
Hitoshi Arai
荒井 斉
Akitsugu Maeda
晃嗣 前田
Takeshi Kano
武司 加納
Toru Higuchi
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2195197A priority Critical patent/JPH0479352A/en
Publication of JPH0479352A publication Critical patent/JPH0479352A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は、半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

特に、電磁波ノイズ対策された半導体装置に関するもの
である。
In particular, it relates to a semiconductor device with countermeasures against electromagnetic noise.

[従来の技術] 半導体装置、特にプラスチック製の半導体パッケージに
半導体素子を搭載し、半導体素子を外界の電磁波ノイズ
から遮蔽し、半導体素子から発生するtvL波ノイズを
も遮蔽することのできる半導体装置が、特開昭64−2
399号公報に開示されている。この半導体装置を第2
図に示す。この半導体装置は、半導体素子3の搭載面の
裏面に形成された金属層8と、半導体素子3の搭載面に
搭載された導電性材料を使用したキッヤブ9と外部接続
用の端子ピン10とを備え、これらが半田12などによ
り電気的に接続されたものであり、これらの電気的接続
により電磁波ノイズを阻止するものである。
[Prior Art] A semiconductor device, in particular, a semiconductor device that mounts a semiconductor element in a plastic semiconductor package, shields the semiconductor element from external electromagnetic wave noise, and can also shield tvL wave noise generated from the semiconductor element. , JP-A-64-2
It is disclosed in Publication No. 399. This semiconductor device is
As shown in the figure. This semiconductor device includes a metal layer 8 formed on the back side of the mounting surface of the semiconductor element 3, a cable plug 9 made of a conductive material mounted on the mounting surface of the semiconductor element 3, and a terminal pin 10 for external connection. These are electrically connected by solder 12 or the like, and these electrical connections block electromagnetic noise.

しかし、 半導体チップの高周波化、高速化により一方
では半導体素子からの電磁波ノイズの発生はますます太
き(なり、他方では半導体装置の小型化によって外界か
らの電磁波ノイズの影響を無視することがますますでき
なくなってきている、そこで、前記の開示技術以上に、
電磁波ノイズに対応できる半導体パッケージからなる半
導体装置が期待されていた。
However, as the frequency and speed of semiconductor chips increase, on the one hand, the generation of electromagnetic wave noise from semiconductor elements is becoming more and more pronounced, and on the other hand, due to the miniaturization of semiconductor devices, it is possible to ignore the influence of electromagnetic wave noise from the outside world. Therefore, in addition to the above-mentioned disclosed technology,
Semiconductor devices made of semiconductor packages that can withstand electromagnetic noise have been expected.

〔発明が解決しようとする課題] 電磁波ノイズにすぐれた半導体パッケージを提供するこ
とにある。
[Problems to be Solved by the Invention] It is an object of the invention to provide a semiconductor package that is excellent in electromagnetic noise.

(課題を解決するための手段〕 本発明は、前記課題を解決するためにプリント配線板か
ら形成されるピングリッドアレイ型の半導体装置におい
て、端子ビン突出部分を除いてプリント配線板の全体が
、プリント配線板の一方の表面に配設された金属層とこ
れに接続してプリント配線板を冠装するキャップからな
る金属体で覆われ、キャップがプリント配線板の端部に
まで展設されたプリント配線板の内層導体パターンと接
続されてなることを特徴とするものである。
(Means for Solving the Problems) In order to solve the above problems, the present invention provides a pin grid array type semiconductor device formed from a printed wiring board, in which the entire printed wiring board except for the protruding portions of the terminal bins is It is covered with a metal body consisting of a metal layer placed on one surface of the printed wiring board and a cap that connects to this and covers the printed wiring board, and the cap extends to the edge of the printed wiring board. It is characterized in that it is connected to an inner layer conductor pattern of a printed wiring board.

〔実施例] 以下、本発明を実施例の図面に基づいて説明する。〔Example] Hereinafter, the present invention will be explained based on drawings of embodiments.

第1図は本発明の一実施例に係る半導体装置の断面図で
あり、このものの平面図(図示せず)の外形は正方形を
している。第1図の半導体装置は、四角形のプリント配
線板1の一方の表面のほぼ中央に形成された半導体素子
の搭載用の凹部2に搭載された半導体素子3、この半導
体素子3を金線など極細のワイヤー4でその凹部2の周
縁部から放射状に配設された導体回路5の端部に接続さ
れ、さらに、この導体回路5はプリント配線板1の外周
縁部の内側に格子状に形成されたスルホル6に接続され
、このスルホール6には外部接続用の端子ピン10が挿
入、半田固着されたものであり、他方の表面は、突出す
る端子ピン10とこの端子ピンが挿入されたスルホール
6のランド11と電気的に絶縁距離をおいて表面全体に
金属箔からなる金属層8が配設され、この金属層8と接
続させて金属体のキャップ9がプリント配線板1および
、半導体素子3を冠装してなり、かつ、このキャップ9
は、プリント配線板1の端部にまで展設された11磁波
シールド効果をもつ内層導体パターン7ともプリント配
線板1の端面で接続されてなる半導体装置である。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and the outer shape of this device in a plan view (not shown) is square. The semiconductor device shown in FIG. 1 includes a semiconductor element 3 mounted in a recess 2 for mounting a semiconductor element formed approximately at the center of one surface of a rectangular printed wiring board 1, and a semiconductor element 3 made of ultra-thin wire such as gold wire. The wires 4 are connected to the ends of conductor circuits 5 arranged radially from the periphery of the recess 2, and the conductor circuits 5 are formed in a grid shape inside the outer periphery of the printed wiring board 1. A terminal pin 10 for external connection is inserted and soldered into this through hole 6, and the other surface is connected to a protruding terminal pin 10 and a through hole 6 into which this terminal pin is inserted. A metal layer 8 made of metal foil is disposed on the entire surface at an electrically insulating distance from the land 11 of the printed wiring board 1 and the semiconductor element 3. and this cap 9
is a semiconductor device in which the end face of the printed wiring board 1 is connected to an inner layer conductor pattern 7 having a magnetic wave shielding effect 11 extending to the end of the printed wiring board 1.

なお、プリント配線板1の端面で接続されない内層導体
パターン7aがプリント配線板lに配設されたものでも
よい。
Note that an inner layer conductor pattern 7a that is not connected at the end surface of the printed wiring board 1 may be provided on the printed wiring board l.

半導体素子3の封止保護も兼ねる金属体のキャップ9は
、このキャップ9の側壁を上記プリント配線板lの端面
に隙間なく接触させて冠装される結果、プリント配線板
1の底面に配設された金属層8、プリント配線板1の端
部にまで展設された電磁波シールド効果をもつ内層導体
パターン7とプリント配線板1の端面で接合されるので
、ノイズに対するシールド効果が一層大きくなるのであ
る。キャップと金属層と内層導体パターンとが電気的に
接続したものを、さらに、端子ピンに接続し、かかる半
導体装置を実装したマザーボードに電磁波ノイズを逃が
すこともできるものである。
The metal cap 9, which also serves as sealing protection for the semiconductor element 3, is mounted on the bottom surface of the printed wiring board 1 as a result of being mounted with the side wall of the cap 9 in close contact with the end surface of the printed wiring board 1. Since the metal layer 8 is bonded to the inner layer conductor pattern 7 extending to the end of the printed wiring board 1 and has an electromagnetic wave shielding effect at the end surface of the printed wiring board 1, the shielding effect against noise is further increased. be. The electrically connected cap, metal layer, and inner layer conductor pattern can be further connected to terminal pins to allow electromagnetic noise to escape to a motherboard on which such a semiconductor device is mounted.

上記のプリント配線板1に冠装された、金属体のキャッ
プ9の内面側に形成されたプリント配線板1との間隙に
例えばエポキシ樹脂、ポリイミド樹脂、シリコン樹脂の
如き液状樹脂の硬化した耐湿性を有するシール材を充填
して、半導体素子が外界から完全に封止保護されるもの
でもよい。
Moisture-resistant hardened liquid resin such as epoxy resin, polyimide resin, or silicone resin is applied to the gap between the printed wiring board 1 and the printed wiring board 1 formed on the inner surface of the metal cap 9 mounted on the printed wiring board 1. The semiconductor element may be completely sealed and protected from the outside world by being filled with a sealing material having the following properties.

次に、使用材料について述べると、第1区の半導体装置
の半導体パッケージを構成するプリント配線板1として
は、基材に樹脂を含浸乾燥して得られたプリプレグの樹
脂が硬化した絶縁材料を用いることができる。ここでプ
リント配線板1の樹脂としては耐熱性、耐湿性に優れか
つ樹脂純度、特にイオン性不純物の少ないものが好まし
い。具体的には、エポキシ樹脂、ポリイミド樹脂、弗素
樹脂、ポリフェニレンオキサイド樹脂などが適している
。なお、プリント配線板1を構成する基材としては、紙
よりガラス繊維などの無機質材料の方が耐熱性、耐湿性
などに優れている点で好ましい。あるいは硬化性樹脂の
成形により得られたプリント配線板を用いることもでき
る。
Next, regarding the materials used, the printed wiring board 1 that constitutes the semiconductor package of the semiconductor device in the first section uses an insulating material made of a prepreg resin obtained by impregnating a base material with a resin and drying it. be able to. Here, the resin for the printed wiring board 1 is preferably a resin that has excellent heat resistance and moisture resistance, and has high purity, especially low ionic impurities. Specifically, epoxy resin, polyimide resin, fluororesin, polyphenylene oxide resin, etc. are suitable. Note that as the base material constituting the printed wiring board 1, an inorganic material such as glass fiber is preferable to paper because it has superior heat resistance, moisture resistance, and the like. Alternatively, a printed wiring board obtained by molding a curable resin can also be used.

プリント配線板1の半導体素子の搭載側の表面の導体回
路5、この反対側の表面の金属層8は、銅、真鍮、アル
ミニウム、鉄、ニッケル、ステンレス箔または、板状物
などから適宜選択して適用でき、中でも銅箔が導電性に
優れ好ましい。また、特に金属層8は別に作成した板状
物を接着層を介してプリント配線板lに配設したもので
あってもよい。
The conductor circuit 5 on the surface of the printed wiring board 1 on which the semiconductor elements are mounted, and the metal layer 8 on the opposite surface are appropriately selected from copper, brass, aluminum, iron, nickel, stainless steel foil, plate-like material, etc. Among them, copper foil is preferred because of its excellent conductivity. Further, in particular, the metal layer 8 may be a separately prepared plate-like material disposed on the printed wiring board l via an adhesive layer.

また、プリント配線板1の半導体素子の搭載側の表面の
導体回路5、スルホール6内の導電路および、この反対
面に配設された金属層8はプリント配線板の加工の一環
として通常の回路形成方法のアディティブ法、サブトラ
クティブ法などによって形成することができる。
Further, the conductor circuit 5 on the surface of the printed wiring board 1 on the side where the semiconductor element is mounted, the conductive path in the through hole 6, and the metal layer 8 disposed on the opposite surface are formed as a normal circuit as part of the processing of the printed wiring board. It can be formed by an additive method, a subtractive method, or the like.

なお、金属層8、内層導体パターン7とキャップ9との
接合は上記の如く直接的な接触状態に限定する趣旨では
なく、導電性の接着剤、例えば銀粉入りのエポキシ樹脂
又は、ポリイミド樹脂の接着剤などが金属層8とキャッ
プ90間、内層導体パターン7とキャップ9の間に導電
路となるように充填された間接的な接続でもよく、電気
的な接続状態が形成されている限り、本発明の課題は解
決される。
Note that the bonding between the metal layer 8, the inner layer conductor pattern 7, and the cap 9 is not limited to direct contact as described above, but may be bonded with a conductive adhesive, such as an epoxy resin containing silver powder or a polyimide resin. An indirect connection in which a conductive agent or the like is filled between the metal layer 8 and the cap 90 or between the inner layer conductor pattern 7 and the cap 9 to form a conductive path may be used, and as long as an electrical connection is formed, the main The problem of the invention is solved.

〔作用〕[Effect]

プリント配線板に搭載された半導体素子を金属体でなる
金属層とキャンプで包み込み、さらに、金属層とプリン
ト配線板の構成材である絶縁層と内層導体パターンとで
構成される一種のコンデンサによって一層1を磁波ノイ
ズを減衰させる効果を生しるのである。
The semiconductor element mounted on the printed wiring board is surrounded by a metal layer made of metal and a camp, and is further enhanced by a type of capacitor composed of the metal layer, an insulating layer, which is the constituent material of the printed wiring board, and an inner layer conductor pattern. 1 has the effect of attenuating magnetic noise.

〔発明の効果] 本発明の構成の半導体装置によって、電磁波ノイズに優
れた半導体パッケージを得ることができるのである。
[Effects of the Invention] With the semiconductor device having the structure of the present invention, a semiconductor package with excellent electromagnetic noise can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図、第2図は一従
来例を示す断面図である。 ・・・プリント配線板 ・・・半導体素子の搭載用の凹部 ・・・半導体素子 ・・・ワイヤー ・・・導体回路 ・・・スルホール 、7a・・・内層導体パターン ・・・金属層 9・・・キャンプ 10・・・端子ピン 11・・・ランド 12・・・半田 第1図 特許出願人  松下電工株式会社
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. ...Printed wiring board...Recess for mounting semiconductor element...Semiconductor element...Wire...Conductor circuit...Through hole, 7a...Inner layer conductor pattern...Metal layer 9...・Camp 10...Terminal pin 11...Land 12...Solder Figure 1 Patent applicant Matsushita Electric Works Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] (1)プリント配線板から形成されるピングリッドアレ
イ型の半導体装置において、端子ピン突出部分を除いて
プリント配線板の全体が、プリント配線板の一方の表面
に配設された金属層とこれに接続してプリント配線板を
冠装するキャップからなる金属体で覆われ、キャップが
プリント配線板の端部にまで展設されたプリント配線板
の内層導体パターンと接続されてなることを特徴とする
半導体装置。
(1) In a pin grid array type semiconductor device formed from a printed wiring board, the entire printed wiring board, excluding the protruding portions of the terminal pins, is connected to a metal layer disposed on one surface of the printed wiring board. It is characterized in that it is covered with a metal body consisting of a cap that connects and covers the printed wiring board, and the cap is connected to the inner layer conductor pattern of the printed wiring board that extends to the end of the printed wiring board. Semiconductor equipment.
JP2195197A 1990-07-23 1990-07-23 Semiconductor device Pending JPH0479352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2195197A JPH0479352A (en) 1990-07-23 1990-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2195197A JPH0479352A (en) 1990-07-23 1990-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0479352A true JPH0479352A (en) 1992-03-12

Family

ID=16337069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2195197A Pending JPH0479352A (en) 1990-07-23 1990-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0479352A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014516212A (en) * 2011-06-09 2014-07-07 アップル インコーポレイテッド Electromagnetic shielding structure for shielding components on the board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014516212A (en) * 2011-06-09 2014-07-07 アップル インコーポレイテッド Electromagnetic shielding structure for shielding components on the board
US9179538B2 (en) 2011-06-09 2015-11-03 Apple Inc. Electromagnetic shielding structures for selectively shielding components on a substrate

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