JPH0479437U - - Google Patents
Info
- Publication number
- JPH0479437U JPH0479437U JP12413090U JP12413090U JPH0479437U JP H0479437 U JPH0479437 U JP H0479437U JP 12413090 U JP12413090 U JP 12413090U JP 12413090 U JP12413090 U JP 12413090U JP H0479437 U JPH0479437 U JP H0479437U
- Authority
- JP
- Japan
- Prior art keywords
- molded
- correspondence
- integrated circuit
- type semiconductor
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図乃至第５図は本考案の実施例を示す斜視
図である。
１……リード番号識別表示記号、２……モール
ド樹脂部、３……リード、４……第１リード表示
記号、５……凹部、６……凸部、７……シルク印
刷、８……リード番号。
1 to 5 are perspective views showing an embodiment of the present invention. 1... Lead number identification display symbol, 2... Molded resin part, 3... Lead, 4... First lead display symbol, 5... Concave portion, 6... Convex portion, 7... Silk printing, 8... Lead number.
Claims (1)
、モールド樹脂部の上面若しくは側面に等間隔で
配列されたリードに対応してリード位置識別表示
を形成するようにしたことを特徴とする半導体集
積回路のパツケージ。 1. A molded package type semiconductor integrated circuit, characterized in that lead position identification indicators are formed on the top or side surface of a molded resin portion in correspondence with the leads arranged at equal intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12413090U JPH0479437U (en) | 1990-11-26 | 1990-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12413090U JPH0479437U (en) | 1990-11-26 | 1990-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0479437U true JPH0479437U (en) | 1992-07-10 |
Family
ID=31871798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12413090U Pending JPH0479437U (en) | 1990-11-26 | 1990-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0479437U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022038870A (en) * | 2020-08-27 | 2022-03-10 | 株式会社東芝 | Semiconductor package and marking method |
-
1990
- 1990-11-26 JP JP12413090U patent/JPH0479437U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022038870A (en) * | 2020-08-27 | 2022-03-10 | 株式会社東芝 | Semiconductor package and marking method |