JPH0479611A - Phase locked loop circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase-locked circuit that extracts a clock from self-synchronized digital data. This is related to something that can prevent synchronization due to ratios.

[Conventional technology]

Conventionally, a phase synchronized circuit for extracting a clock from self-synchronized digital data has had a circuit configuration as shown in FIG. That is, digital data is inputted from the terminal 1 and converted into a logic level by the voltage comparison circuit 2.

Negative feedback is generally applied to the comparison voltage of the voltage comparison circuit so that it becomes the optimum value, and in this case, it is called slice level control. In the phase/frequency comparison circuit 3, the outputs of the voltage controlled oscillator 6 and the voltage comparison circuit 2 are compared in phase/frequency, and the output is amplified by the DC amplifier 4 and passed through the low pass filter 5 to the output of the voltage controlled oscillator 6. becomes the control voltage,
A phase-locked loop is constructed.

If the phases are synchronized, the input data is latched by the latch circuit 7 using the output of the voltage controlled oscillator 6 as a clock, and synchronized data and clock are obtained at the output terminals 8 and 9, respectively. An example of the data and clock waveforms is shown in FIG. The phase/frequency comparator 2 generally has a changing point detection function because the input digital data is not a continuous periodic signal but contains clock information at changing points. In addition, when the frequency change range of input data is wide, it is common to have a frequency comparison function as well.

[Problem to be solved by the invention]

Conventional phase-locked circuits of this type were constructed as described above, and had the following problems.

In other words, when the frequency change range of the input data and the oscillation frequency of the voltage controlled oscillator are wide, if a fixed pattern continues in the input data, the loop will enter a state of incorrect synchronization at a frequency different from the frequency that should be synchronized, and the data will become erroneously synchronized. This is because a so-called false image lock phenomenon to spurious frequencies occurs, which makes demodulation impossible.

The most extreme example is shown in Figure 5. If the data is continuous in a fixed pattern and the output of the voltage controlled oscillator that should be synchronized is the waveform of clock 1 in the figure, then the data in the figure On the other hand, even the waveform of clock 2 will be synchronized. To prevent this kind of phenomenon from occurring, data is generally filtered or a frequency comparison function is provided in the phase comparator circuit, but even if such measures are taken, for example, 11 to 12, etc. 13
14, when the frequency ratio is close to 1 and has an integer-to-integer ratio relationship with the frequency to which synchronization should be performed, there is a possibility that false synchronization may occur at these frequency ratios. Particularly when frequency comparison is performed digitally, the gain of frequency comparison is generally small or zero in a portion where the frequency ratio is close to 1.

The present invention has been made in view of this point, and when extracting clocks from self-synchronized digital data,
It is an object of the present invention to provide a phase synchronization circuit that has a low probability of falling into erroneous synchronization.

[Means for Solving the Problems] A phase-locked circuit according to the present invention includes a voltage comparator circuit, a voltage controlled oscillator, a comparator that compares the phase/frequency of their outputs, and a phase/frequency comparator output. An offset is applied to the output voltage of the phase/frequency comparator circuit during the phase-locked loop transition from an asynchronous state to a synchronous state. An offset applying circuit is provided to apply an offset during the transition of the phase-locked loop from an asynchronous state to a synchronous state.

[Operation] Since the present invention is configured as described above, the probability of falling into erroneous synchronization can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a phase locked circuit according to an embodiment of the present invention,
In the figure, ■ is a data input terminal, 2 is a voltage comparison circuit, 3 is a phase/frequency comparison circuit, 4 is a DC amplifier, 5 is a low-pass filter, 6 is a voltage controlled oscillator, and each of the above configurations The elements form a phase-locked loop. 7 is a latch circuit, which outputs synchronized data and a clock to output terminals 8.9. 10 is an offset application circuit, and 11 is a signal generation circuit indicating a transition period from an asynchronous state to a synchronous state.

Next, the operation will be explained. When the phase-locked loop is in a normal synchronized state, it operates in the same way as the conventional example shown in FIG. However, an offset is applied to the output voltage of the phase comparison circuit only in the process of transitioning from an asynchronous state to a synchronous state. Compared to the frequency that should originally be synchronized, the spurious frequency that causes false synchronization has a small response, and even a slight disturbance such as an offset can prevent false synchronization from occurring.

Various circuits can be used as the signal generation circuit 11 for generating the signal indicating that it is the transition period from the asynchronous state to the synchronous state, depending on the system in which the phase locked circuit is used. For example, in a compact disc player, in a phase synchronized circuit that extracts a clock from an EFM (8→14) modulated signal,
A signal indicating a playback start state can be used. For example, a disc motor start signal outputted from a system control microcomputer, a track jump signal, or in some cases an audio muting signal can be used.

In addition to the above-mentioned effect as a disturbance, the application of the offset has the following effects. When the frequency comparison part of the phase/frequency comparison circuit 3 is configured with a digital circuit, it generally depends on whether the oscillation frequency of the voltage controlled oscillator 6 enters synchronization from a high state or a low state with respect to the frequency of the input data. The probability of falling into false synchronization is different. In the case of the EFM signal of a compact disc player, the reversal period is from 3T to LIT.
It is in. Therefore, when frequency comparison is performed by a counter at half the period T, the detection ability is 2.5T or less, 11
．． It will be 5T or more. That is, 11°5/11=104.
5% and 2.5T/3T→83.3%, the width of the dead zone in the frequency comparison operation differs above and below the synchronous frequency. If the offset application direction is set so that the direction from the asynchronous state to the synchronous state is the direction in which the width of the dead zone is narrow, the probability of falling into erroneous synchronization can be further reduced.

In addition, in FIG. 1, except for the three phase frequency comparator circuits, the offset application portion is configured so as to have the same effect.
Offcents can also be applied to other parts within the loop, such as the DC amplifier 4. Similar effects can also be obtained when an offset is applied to the voltage comparator circuit 2. 6th
Figures (a) and (b) show the input and output voltage waveforms of the voltage comparison circuit. C is a comparison voltage. The voltage waveform obtained by applying an offset to this comparison voltage is shown in Fig. 7 (a) and (g)).
As is clear from the figure, there is an effect similar to that of adding jitter to the output voltage (b).

FIG. 2 shows another embodiment of the present invention in which a synchronization pattern detection circuit 12 is added to the circuit shown in FIG. However, at that point, the application of the offset is stopped.

〔Effect of the invention〕

As described above, according to the present invention, when a clock is extracted from self-synchronous data using a phase-locked loop, an offset is applied to the phase-locked loop during the transition period from an asynchronous state to a synchronous state. This has the effect of preventing a fall into erroneous synchronization.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing a phase-locked circuit according to one embodiment of the present invention, FIG. 2 is a diagram showing a phase-locked circuit according to another embodiment of the present invention, and FIG. 3 is a diagram showing a conventional phase-locked circuit. A diagram showing a phase-locked circuit by example,
FIG. 4 is a diagram showing output data and output clock waveforms of the phase synchronization circuit, FIG. 5 is a diagram showing waveforms representing erroneous synchronization,
6(a) and (1)) are diagrams showing input waveforms and output waveforms of the voltage comparison circuit, and FIG. 7 is a waveform diagram showing a state in which an offset is applied to FIG. 6. In the figure, 1 is a signal input terminal, 2 is a voltage comparison circuit, and 3 is a signal input terminal.
is a phase/frequency comparator, 4 is a DC amplifier, 5 is a low-pass filter, 6 is a voltage controlled oscillator, 7 is a crawler circuit, 8 is a data output terminal, 9 is a clock output terminal, 1O is an offset application circuit, 11 is an asynchronous to synchronous transition signal circuit, 1
2 is a synchronization pattern detection circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A phase-locked circuit that extracts a clock from self-synchronous digital data, which includes a voltage comparison circuit that converts an input signal to a logic level, a voltage-controlled oscillator that oscillates at a frequency according to the control voltage, and the voltage comparison circuit described above. and a phase/frequency comparator that compares the phase and frequency of the output of the voltage-controlled oscillator, a DC amplifier and a low-pass filter that amplify and filter the output and apply it as a control voltage to the voltage-controlled oscillator. and an offset application circuit that applies an offset to the output voltage of the phase/frequency comparator in the process of transitioning the phase-locked loop from an asynchronous state to a synchronous state. circuit.