JPH0479627A - System for transferring independent synchronous data - Google Patents

Abstract

PURPOSE:To transfer independent synchronous data without error by sending data with (n) sub-frames unit switching the sub-frames to network clocks, sending dummy bits regarding shortage bits, receiving the data by the network clocks at the reception side, and taking frame synchronization discarding the dummy bits and restoring the sub--frames. CONSTITUTION:By supplying network clock timing from a line interface section 6, a transmitting-side network clock control section 5 reads out data from each frame by means of network clocks by the number of effective data bits in each frame against a sending data clock switching section 4. The data are outputted to the interface section 6 after switching it to the network clocks and sending to a high-speed line. At the time of reception, a frame synchronization processing section 7 detects frame synchronization and informs a reception side network clock controlling section 8 of frame effective area information. At the section 8, effective reception data are successively buffered in a reception data clock switching section 9 in a frame-controlled form based on the network clocks and frame effective area information.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data transfer method for a time division multiplexing device.
In particular, the present invention relates to an independent synchronous data transfer method that is effective for a system in which a time division multiplexer is operated without being dependent on the network clock of a high-speed line.

BACKGROUND OF THE INVENTION Conventionally, high-speed line data transfer in a time division multiplexing apparatus has operated in a manner dependent on the network clock of the high-speed line.

In addition, in the case of time division multiplexing equipment that can accommodate multiple high-speed lines, data transfer on all high-speed lines is performed depending on the network clock of one high-speed line. .

Problems to be Solved by the Invention However, with the above-mentioned high-speed line data transfer method of the conventional time division multiplexer, if the network clock has a frequency deviation exceeding the tarlock pull-in range of the time division multiplexer, it becomes impossible to follow the network clock. However, in the case of a time division multiplexing device that can accommodate multiple high-speed lines, the network clock of any one high-speed line is dependent on the network clock of the subordinate high-speed line. If there is a frequency error between the network clock of the high-speed line and the network clock of the other high-speed line, data slips may occur in data transfer on the other high-speed line.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a new independent synchronization-data transfer system which makes it possible to overcome the above-mentioned drawbacks inherent in the prior art.

Means for Solving the Problems In order to achieve the above object, the independent synchronous data transfer system according to the present invention operates an internal clock in a time division multiplexing device having an internal oscillator without depending on the network clock of a high-speed line. In a system where the internal clock has a higher frequency when comparing the internal clock and the network clock, n
Assuming that is an arbitrary integer, on the transmitting side, the frame synchronization bits and multiplexed data of frames or subframes in the device must be less than or equal to the number of bits that can be transmitted by the network clock per frame period of the multiplexed frame by the internal clock. By prohibiting allocation, when switching to the network clock, only the valid data of each frame or each subframe is buffered for n frames or n subframes using the internal clock, and the buffered data is sent out using the network clock. The time it takes for the next n frames or n subframes of valid data to be buffered after the end of transmission, that is, the number of bits that are insufficient for valid data relative to the number of bits that can be sent by the network clock per n frame or n subframe period by the internal clock. Dummy data is sent by the network clock at the transmission time of the number, and for bit corrections below the decimal point that cannot be corrected by integer data using dummy data in the period of n frames or n subframes, dummy data is sent at a period of more than twice the period of n frames or n subframes. It has means for controlling the number of bits plus or minus, and on the receiving side, receives data with dummy data added in units of n frames or n subframes using a network clock,
Frame synchronization of received data is detected using the network clock, and when switching the received data from the network clock to the internal clock, only the valid data part of n frames or n subframes is buffered, excluding dummy data, and the buffered The device is configured to read valid data frame by frame using an internal clock, and since the prohibited area is not transferred on the transmitting side, a means is provided to reproduce the frame by inserting a dummy after reading the valid data.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, based on the output clock of the internal oscillator 1, the internal clock control section 2 generates various timings within the device. A multiplexed frame is assembled and transmitted according to the timing. However, in this case, the deletion within the multiplexed frame is limited to less than the number of bits that can be transmitted at the network clock timing per frame cycle time of the multiplexed frame. The sending data clock switching unit 4 buffers only the data other than the allocation-prohibited portion of the multiplexed frame, which is partially prohibited from being allocated, in a frame-managed manner according to the timing from the internal clock control unit 2. . On the other hand, the transmitting side network clock control section 5 receives the network clock timing from the line interface section 6, and transmits the network clock to the sending data clock switching section 4 by the number of effective data bits in the frame for each frame. When n frames have been read, the next rl frame data is read out by the network clock for the number of bits that are insufficient to the number of bits that should be sent by the network clock per n frame cycle time by the internal clock. Wait for it to be set.

However, the number of bits to be sent by the network clock per n frame cycle time by the internal clock is rarely an integer, and considering the presence of jitter, for example, if the jitter is less than ±1 bit, reads with a period of 3n frames and corrects the number of read-prohibited bits by the network clock to +1.01-1 for each n frame.
After the transmission data is transferred to the network clock in this manner, it is output to the line interface unit 6, and then sent from the line interface unit 6 to the high-speed line.

Conversely, when receiving data, the frame synchronization processing section 7 detects frame synchronization based on the receiving network clock from the line interface section 6, and notifies the receiving side network clock control section 8 of frame valid area information.

The receiving side network clock control unit 8 buffers the valid data of the received data in the received data clock switching unit 9 in a frame-managed manner based on the network clock and frame valid area information. The internal clock control unit 2 uses the internal clock to read the number of valid data bits for each frame, and stops reading the number of invalid data bits to reproduce the multiplexed frame to the internal frame length, and passes it to the multiplexing/demultiplexing unit 3. , multiplexing/separating section 3
Then, multiplexed frames are received and separated according to the internal clock timing from the internal clock control section 2.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, each frame or each subframe is used such that the number of bits that can be transmitted by the network clock is less than or equal to the number of bits that can be transmitted by the network clock per frame or subframe period period of the multiplexed frame by the internal clock. A prohibited part is provided, and on the transmitting side, when switching from the internal clock to the network clock, the prohibited part of each frame or each subframe is discarded, and the transmitter switches to the network clock in units of n frames or n subframes and sends them, and the missing bits are transmits dummy bits, the receiving side receives data using the network clock, performs frame synchronization, and discards the dummy bits when switching from the network clock to the internal clock. By inserting the discarded prohibited part and restoring the frame or subframe, there is no need to depend on the network clock when the internal clock has a higher frequency than the network clock, so it is possible to limit the clock pull-in range. In addition, in the case of a plurality of high-speed lines, data can be transferred without error in all high-speed lines without being dependent on the network clock of any high-speed line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Internal oscillation section, 2... Internal clock control section, 3
... multiplexing/demultiplexing unit, 4... transmission data clock switching unit, 5... transmitting side network clock control unit, 6... line interface unit, 7... frame synchronization processing unit,
8...Receiving side network clock control unit, 9...Receiving data clock switching unit

Claims (1)

[Claims] In a time division multiplexing device having an internal oscillator, the internal clock is operated independently of the network clock of a high-speed line, and when the internal clock and the network clock are compared, the internal clock has a higher frequency. In a system that By prohibiting the allocation of frame synchronization bits and multiplexed data, when switching to the network clock, only the valid data of each frame or each subframe is buffered for n frames or n subframes using the internal clock. Data is sent using the network clock, and the time until the next n frames or n subframes worth of valid data is buffered after the end of transmission, that is, the data is sent using the network clock every n frame or n subframe period based on the internal clock. Dummy data is sent by the network clock at the sending time of the number of valid data insufficient bits for the available number of bits, and n frames or n
To correct the bits below the decimal point that cannot be corrected by integer data using dummy data in the subframe period, there is a means to perform plus/minus control of the number of dummy data transmission bits at a period of n frames or more than twice the n subframes, and on the receiving side, Data with dummy data added in units of n frames or n subframes is received using the network clock, frame synchronization of the received data is detected using the network clock, and dummy data is added when switching the received data from the network clock to the internal clock. Only the valid data portion of n frames or n subframes are buffered, and the valid data is read out frame by frame using the internal clock, and the prohibited area is not transferred on the transmitting side, so the valid data is not transferred. 1. An independent synchronous data transfer system for a time division multiplexing device, characterized in that the method includes means for reproducing a frame by inserting a dummy after the reading of the frame is completed.