JPH0479633A - Frame synchronization circuit - Google Patents

Abstract

PURPOSE:To properly count frame pulse errors and to monitor the state of frame pulses by invalidating the output of a memory inputoutput comparator circuit by means of an OR circuit and only monitoring the output of a received- signal comparator circuit when the frame pulses are monitored in a synchronized state. CONSTITUTION:The synchronized state of frames is monitored by shifting to a synchronized state by setting a signal (i) indicating the synchronized/non- synchronized state of frames to '1' and comparing frame pulse retrieving pulses (h) with frame pulse comparing output signals (d) at regular intervals. At the time of monitoring, frame pulse comparing output signals (b) from an OR circuit 8 are held in '1' and the same signals as frame pulse comparing output signals (c) become the signals (d). The signals (c) are a compared output between the input signal (a) of a memory circuit 1 and the output signal (e) of a frame counter. The signal (e) is a signal which is inverted to '1' or '0' at every frame and is synchronous to frame signals. Therefore, the signals (c) become '1' when receiving pulse signals are properly received and '0' when the pulse signals are improperly received.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frame synchronization circuit that synchronizes to a frame code in a serial signal having a frame structure, and particularly relates to a frame synchronization circuit that synchronizes with a frame code in a serial signal having a frame structure. This invention relates to a frame synchronization circuit that simultaneously detects frame pulses.

[Conventional technology]

An example of a frame-structured signal is shown in FIG.

In this Figure 2, F and F are frame codes, and D
1 to Dn are data signals. This 7-lem code F, F
is, for example, a repeating pattern of rlJ and rOJ. Then, on the receiving side, the data signal and frame code are separated by specifying and synchronizing the position of the frame code.

An example of a conventional frame synchronization circuit is shown in FIG. 3 and will be described.

In FIG. 3, 11 and 12 are cascade-connected memory circuits, 13 is an exclusive OR circuit which receives the output of this memory circuit 11 and the input signal a of the memory circuit which is a received signal, and 14 is a memory circuit. 15 is an AND circuit that receives the output of exclusive OR circuit 14 and the output of exclusive OR circuit 13; 16 is a frame; Synchronous counter circuit 17 is 7 from this frame synchronized counter circuit 16
v-m pulse search pulse C and logic fft circuit 15! 18 is a counter that counts the frame pulse detection signal d from the AND circuit 15; 19 is a counter that receives the frame pulse comparison output signal d from the AND circuit 15; 20 is an AND circuit that receives the output of this NOT circuit 19 and the frame pulse search pulse C from the frame synchronization counter 16; 21 is a counter that counts frame error detection signals e; 22 is a frame error circuit; It is an AND circuit that receives the detection signal e and the output of the counter 21 as input, and is configured so that the output of the AND circuit 22 is introduced into the counter 18 . 23 is an R/S which is set by the output of the counter 18 and reset by the output of the counter 21.
The output of the R/S flip-flop circuit 23 is introduced into a frame synchronization counter circuit 16, and is configured to output a monitoring output signal f indicating a synchronous/asynchronous state to the outside.

In order to find a frame code, a code that repeats rlJ and rOJ at one frame interval can be monitored and identified, but the search takes time.

Therefore, as shown in FIG. 3, the signal is delayed by a memory circuit 11.12 having a frame length of one frame or more, and each input/output of this memory circuit 11.12 is connected to an exclusive OR circuit. Compare with 12°13 comparison circuit,
By searching for the position of the frame code from the output signal of this comparison circuit, the search can be performed simultaneously over a plurality of frames in an equalizing manner, and synchronization can be achieved in a short time.

[Problem to be solved by the invention]

In this conventional frame synchronization circuit, when a code error occurs in a frame pulse, the comparison result with the previous edge frame pulse becomes inconsistent, so no consecutive frame pulse errors occur, and the frame w@ There was a problem that b was enlarged and counted.

[Means to solve the problem]

The frame synchronization circuit of the present invention is a frame synchronization circuit that synchronizes with a frame code in a serial signal having a frame structure, and is a circuit that compares and matches the input and output codes of this memory circuit with a memory circuit whose code length is the same as the frame length. a first comparison circuit that compares the input signal of the memory circuit and the output of the frame synchronization counter circuit; a second comparison circuit that compares the input/output signal of the memory circuit; The first comparison circuit has an output from the first comparison circuit and the output from the synchronization state monitoring circuit as inputs, and an AND circuit receives the output from the first comparison circuit and the logic circuit as inputs.

[Effect]

In the present invention, when monitoring frame pulses in a synchronous state, the output of the memory input/output comparison circuit is disabled by an OR circuit,
Only the output of the received signal comparison circuit is monitored.

〔Example〕

Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of a frame synchronization circuit according to the present invention.

In FIG. 1, 1 and 2 are memory circuits with the same code length as the frame length, 3 is a frame synchronization counter circuit, and 4 is the input signal a of the memory circuit, which is a received signal, and the frame counter output from the frame synchronization counter circuit 3. This exclusive OR circuit 4 receives the signal e as an input, and the exclusive OR circuit 4 receives the input signal of the memory circuit 1 and the frame synchronization counter circuit 3.
5 constitutes a comparison circuit that compares the outputs of the memory circuit 1, and 6 is an exclusive OR circuit which receives the output of the memory circuit 1 and the input signal a of the memory circuit, which is the received signal, and 6 is the respective output of the memory circuits 1 and 2. is an exclusive OR circuit which receives as input, and constitutes a comparison circuit that compares each input/output signal of memory circuits 1 and 2. 7 is an exclusive OR circuit 5 which is this comparison circuit.
．． 6 is an AND circuit which receives each output as input, and 8 is a logic whose inputs are the output from the comparison circuit consisting of exclusive OR circuits 5 and 6, which are the outputs of this AND circuit T, and the output of the synchronization state monitoring circuit. OR circuit which is a circuit, 9 is exclusive OR circuit 4
This is an AND circuit which receives as inputs the frame pulse comparison output signal C of the comparison circuit consisting of the comparator circuit 8 and the frame pulse comparison output signal S output from the logic circuit consisting of the OR circuit 8.

10 is an AND circuit which receives the frame pulse comparison output signal d from the AND circuit 9 and the frame pulse search pulse h from the frame synchronization counter circuit 3; 11 is the frame pulse comparison output signal d from the AND circuit 9; 12 is a counter that counts the frame pulse detection signal f of the AND circuit 10; 13 is an AND circuit that receives the frame pulse search pulse h from the frame synchronization counter circuit 3 and the output of the NOT circuit 11 as input; A circuit 14 is a counter 1 that counts the output of the AND circuit 13 and the frame error detection signal g which is the output of the frame synchronization counter circuit 3.
5 is an AND circuit that receives the output of this counter 14 and the frame error detection signal g, and 16 is an R/S flip-flop circuit that is set by the output of the counter 12 and reset by the output of the counter 14, and these are synchronized. A state monitoring circuit 17 is configured.

The output of the R/S flip-flop circuit 16 is introduced to the frame synchronization counter circuit 3, and the output of the synchronization state monitoring circuit 17 is led to the OR circuit 8, and a monitoring output signal i indicating the frame synchronization/asynchronous state It is configured to be sent externally as

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, when searching for a frame pulse, the monitoring output signal l indicating the frame synchronization/asynchronous state is not at the "0" level, the frame synchronization counter circuit 3 is shifted by 1 bit, and the outputs of the exclusive OR circuits 4, 5.6 are Find all matching bits. A frame pulse comparison output signal d at a bit position one frame after the searched bit is monitored using a frame pulse search pulse h. If a frame pulse is detected in the frame pulse detection signal f, the bits one frame later are further monitored. When a frame error is detected in the frame error detection signal g, a bit that is considered to be the next frame pulse is searched for while shifting by one bit.

Next, when frame pulses are detected continuously and the counter 12 counts up to a full count due to the frame pulses being detected, the R/S flip-flop circuit 16 is set to generate a signal 1 indicating the frame synchronization/asynchronous state. "1
'', the synchronization state is entered, and the synchronization state is monitored by comparing the frame pulse search pulse h and the frame pulse comparison output signal d at regular intervals.

In this case, the frame pulse comparison output signal S from the OR circuit 8 is held at "1", and the same signal as the frame pulse comparison output signal C appears as the frame pulse comparison output signal d.

The frame pulse comparison output signal C is a comparison output of the received signal input signal a of the memory circuit 1 and the 7-frame counter output signal e, and this frame counter output signal e is "1" for each frame.

It is assumed that the signal is an inverted "0" signal and is synchronized with the frame signal.

Therefore, the frame pulse comparison output signal C becomes "1" if the received pulse code is correctly received fc, and becomes "0" if it is incorrect. If a frame pulse causes an error, the error pulse is counted only once, and the next frame pulse is not counted as an error pulse.

〔Effect of the invention〕

As explained above, in the present invention, when frame pulses are monitored in a synchronous state, the output of the memory input/output comparison circuit is disabled by the OR circuit, and only the output of the received signal comparison circuit is monitored, so that the frame pulse code is In the event of an error, the frame pulses before and after are regarded as error pulses and are not magnified and counted. This has the effect of correctly counting frame pulse errors and monitoring the status.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a frame synchronization circuit according to the present invention, FIG. 2 is a diagram 8A showing an example of a frame-structured signal, and FIG. 3 is an example of a conventional 7-frame synchronization circuit. It is a circuit block diagram showing. 1.2--Memory circuit, 3--e frame synchronization counter circuit, 4 to 6, fist/Φ exclusive OR circuit (comparison circuit), 8...OR circuit (logic circuit), 9.Fist・-
AND circuit, 17・−〇・Synchronization state monitoring circuit. Patent applicant: NEC Corporation Shizuoka NEC Corporation Agent Masaki Yamazuki

Claims (1)

[Claims] A frame synchronization circuit that synchronizes with a frame code in a serial signal having a frame structure, and has a memory circuit having a code length that is the same as the frame length, and a circuit that compares and matches the input and output codes of this memory circuit. A first comparison circuit that compares the input signal of the memory circuit and the output of the frame synchronization counter circuit, a second comparison circuit that compares the input/output signal of the memory circuit, and synchronization with the output from the second comparison circuit. A frame synchronization circuit comprising: a logic circuit that receives the output of the state monitoring circuit; and an AND circuit that receives the output of the first comparison circuit and the output of the logic circuit.