JPH0480064U - - Google Patents
Info
- Publication number
- JPH0480064U JPH0480064U JP1990125611U JP12561190U JPH0480064U JP H0480064 U JPH0480064 U JP H0480064U JP 1990125611 U JP1990125611 U JP 1990125611U JP 12561190 U JP12561190 U JP 12561190U JP H0480064 U JPH0480064 U JP H0480064U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- circuit pattern
- semiconductor device
- view
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
Landscapes
- Wire Bonding (AREA)
Description
第１図は、この考案の一実施例である半導体装
置の組立状態を示す斜視図、第２図は第１図のワ
イヤの接続状態を示す部分拡大断面正面図、第３
図は第１図の半導体装置の製造方法を示すフロー
チヤート、第４図、第５図はは半導体素子Ａ，Ｂ
のウエハの状態を示す平面図、第６図は第１図の
半導体装置の展開斜視図、第７図は従来の半導体
装置の平面図、第８図は第７図のワイヤの接続状
態を示す部分拡大断面正面図である。
１……基板、２……チツプＢ、３……凹部７に
設けられた回路パターンＡ、４……電極、５……
配線部、６ａ……Ａｕワイヤ、７……凹部、８ａ
，８ｂ……ウエハ、なお、図中、同一符号は同一
、又は相当部分を示す。
1 is a perspective view showing an assembled state of a semiconductor device which is an embodiment of this invention; FIG. 2 is a partially enlarged sectional front view showing a state of connection of wires in FIG.
The figure is a flowchart showing a method for manufacturing the semiconductor device in Figure 1, and Figures 4 and 5 are for semiconductor elements A and B.
6 is an exploded perspective view of the semiconductor device in FIG. 1, FIG. 7 is a plan view of a conventional semiconductor device, and FIG. 8 is a diagram showing the state of the wire connections in FIG. 7. FIG. 3 is a partially enlarged sectional front view. 1...Substrate, 2...Chip B, 3...Circuit pattern A provided in recess 7, 4...Electrode, 5...
Wiring part, 6a... Au wire, 7... Recessed part, 8a
, 8b... wafer. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ーンを形成し、前記凹部に異なつた回路パターン
Ａを表面に形成した半導体素子Ｂを接合し、前記
半導体Ａ，Ｂを電気的に結線することにより、小
さな面積で、複数の半導体素子を組み合わせるこ
とができるようにしたことを特徴とする半導体装
置。 By forming a circuit pattern in the recess of a substrate having a recess on its surface, bonding a semiconductor element B having a different circuit pattern A on its surface to the recess, and electrically connecting the semiconductors A and B. A semiconductor device characterized by being able to combine multiple semiconductor elements in a small area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990125611U JPH0480064U (en) | 1990-11-27 | 1990-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990125611U JPH0480064U (en) | 1990-11-27 | 1990-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480064U true JPH0480064U (en) | 1992-07-13 |
Family
ID=31873203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990125611U Pending JPH0480064U (en) | 1990-11-27 | 1990-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480064U (en) |
-
1990
- 1990-11-27 JP JP1990125611U patent/JPH0480064U/ja active Pending