JPH0480133U

JPH0480133U -

Info

Publication number: JPH0480133U
Application number: JP12367490U
Authority: JP
Priority date: 1990-11-27
Filing date: 1990-11-27
Publication date: 1992-07-13

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のトライステートバ
ツフア素子の回路図、第２図は従来のトライステ
ートバツフア素子の回路図、第３図は第２図の回
路の動作タイミングチヤート、第４図は従来の標
準的なコンピユータシステムのバス線まわりの回
路図、第５図は第１図の回路の動作タイミングチ
ヤートである。１，４〜６……インバータ回路、２，３ａ，７
，１１……ノアゲート回路、８，９……トランジ
スタ、１０……デイレイ素子。 Fig. 1 is a circuit diagram of a tri-state buffer element according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional tri-state buffer element, Fig. 3 is an operation timing chart of the circuit shown in Fig. 2; FIG. 4 is a circuit diagram around the bus line of a conventional standard computer system, and FIG. 5 is an operation timing chart of the circuit shown in FIG. 1. 1, 4-6...Inverter circuit, 2, 3a, 7
, 11...Nor gate circuit, 8, 9...Transistor, 10...Delay element.

補正平３．４．２６考案の名称を次のように補正する。考案の名称トライステートバツフア素子実用新案登録請求の範囲、図面の簡単な説明を
次のように補正する。Amendment 3.4.26 The name of the invention is amended as follows. Title of the invention: Tri-state buffer element The scope of the utility model registration claims and the brief description of the drawings are amended as follows.

【実用新案登録請求の範囲】ゲート信号の有効時に入力信号に従つて出力を
第１又は第２の論理レベルに駆動し、ゲート信号
の無効時に出力をハイインピーダンスにするトラ
イステートバツフア素子において、ゲート信号の有効時に出力を第１の論理レベル
に駆動する第１のスイツチング素子と、ゲート信号の有効時に出力を第２の論理レベル
に駆動する第２のスイツチング素子と、ゲート信号の有効から無効への変化により一定
時間幅のパルス信号を出力して前記第１又は第２
の一方のスイツチング素子を強制導通させる強制
回路とを備えたことを特徴とするトライステート
バツフア素子。[Claims for Utility Model Registration] A tri-state buffer element that drives an output to a first or second logic level according to an input signal when a gate signal is valid, and makes the output high impedance when the gate signal is invalid, a first switching element that drives the output to a first logic level when the gate signal is valid; a second switching element that drives the output to the second logic level when the gate signal is valid; A pulse signal of a certain time width is outputted by the change in the first or second pulse signal.
A tri-state buffer element comprising: a forced circuit that forcibly brings one switching element into conduction.

【図面の簡単な説明】第１図は本考案の一実施例のトライステートバ
ツフア素子の回路図、第２図は従来のトライステ
ートバツフア素子の回路図、第３図は第２図の回
路の動作タイミングチヤート、第４図は従来の標
準的なコンピユータシステムのバス線まわりの回
路図、第５図は第１図の回路の動作タイミングチ
ヤートである。１，４〜６……インバータ回路、２，３ａ，７
，１１……ノアゲート回路、８，９……トランジ
スタ、１０……デイレイ素子。[Brief Description of the Drawings] Fig. 1 is a circuit diagram of a tri-state buffer element according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional tri-state buffer element, and Fig. 3 is a circuit diagram of a tri-state buffer element according to an embodiment of the present invention. 4 is a circuit diagram of a conventional standard computer system around a bus line, and FIG. 5 is an operation timing chart of the circuit shown in FIG. 1. 1, 4-6...Inverter circuit, 2, 3a, 7
, 11...Nor gate circuit, 8, 9...Transistor, 10...Delay element.

Claims

[Claims for Utility Model Registration] A tri-state buffer element that drives an output to a first or second logic level according to an input signal when a gate signal is valid, and makes the output high impedance when the gate signal is invalid, a first switching element that drives the output to a first logic level when the gate signal is valid; a second switching element that drives the output to the second logic level when the gate signal is valid; A pulse signal of a certain time width is outputted by the change in the first or second pulse signal.
A tri-state buffer element comprising: a forced circuit that forcibly brings one switching element into conduction.