JPH0480135U

JPH0480135U -

Info

Publication number: JPH0480135U
Application number: JP12459590U
Authority: JP
Priority date: 1990-11-27
Filing date: 1990-11-27
Publication date: 1992-07-13

Description

[Brief explanation of the drawing]

第１図は本考案を実施した縦続積分型Ａ／Ｄ変
換器の要部構成図、第２図は積分器の逆積分時間
と比較器の反転タイミングの関係を示す図、第３
図は第１の比較器のオフセツトが負側で大きい場
合の逆積分の状態を示す図、第４図は一般的な縦
続積分型Ａ／Ｄ変換回路の構成図、第５図は第４
図に示す変換回路の動作説明図である。１……積分器、２１，２２，２３……電流源、
３……第１の比較器、４……インターフエイス、
５……９ビツト上位カウンタ、６……第２の比較
器、７……７ビツト下位カウンタ、８……シフト
・レジスタ、９……制御回路、Ｓ１，Ｓ２，Ｓ３
，Ｓ４……スイツチ、Ｒ……抵抗、２０……時間
計測手段（ロジツクアナライザ）。 Figure 1 is a diagram showing the main parts of a cascade-integrating A/D converter embodying the present invention, Figure 2 is a diagram showing the relationship between the inverse integration time of the integrator and the reversal timing of the comparator, and Figure 3 is a diagram showing the relationship between the inverse integration time of the integrator and the inversion timing of the comparator.
The figure shows the state of inverse integration when the offset of the first comparator is large on the negative side, FIG. 4 is a configuration diagram of a general cascade integration type A/D conversion circuit, and FIG.
FIG. 3 is an explanatory diagram of the operation of the conversion circuit shown in the figure. 1... Integrator, 21, 22, 23... Current source,
3...first comparator, 4...interface,
5... 9-bit upper counter, 6... second comparator, 7... 7-bit lower counter, 8... shift register, 9... control circuit, S1, S2, S3
, S4... Switch, R... Resistor, 20... Time measuring means (logic analyzer).

Claims

[Scope of utility model registration request]

The analog input signal is integrated by an integrator at a constant timing T, and this integrated value is inversely integrated by applying a current I+i (current ratio I/i=2 ⁿ -1; n is the number of bits of the lower counter described later). The time T3 until the set value of the first comparator is reached is counted by the upper counter, and then the time T4 until the set value of the second comparator is reached by applying the current i and inversely integrated is counted by the lower counter. , a cascade integral type A/D converter that obtains a digital signal corresponding to the analog input signal from a time value T3 and a time value T4, wherein the first and second
A cascade integration type A/D conversion characterized by providing means for branching the output of the comparator and taking it out to the outside, and means for measuring the time Tu, Tl from the inverse integration start timing until each comparator is inverted. vessel.