JPH0480148U - - Google Patents
Info
- Publication number
- JPH0480148U JPH0480148U JP12357090U JP12357090U JPH0480148U JP H0480148 U JPH0480148 U JP H0480148U JP 12357090 U JP12357090 U JP 12357090U JP 12357090 U JP12357090 U JP 12357090U JP H0480148 U JPH0480148 U JP H0480148U
- Authority
- JP
- Japan
- Prior art keywords
- shows
- signals
- ability
- utility
- model registration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Logic Circuits (AREA)
Description
第１−１図は、記憶理論、第１−２は記憶理論
論理、第１−３図は入力波形、第１−４図は出力
波形、第２−１図は記憶理論メモリ、第２−２図
は、入力波形、第２−３図は、Ｃ出力波形、第２
−４図はＤ出力波形、第３−１図は、Ｎ個入力記
憶理論メモリ。
論理、第１−３図は入力波形、第１−４図は出力
波形、第２−１図は記憶理論メモリ、第２−２図
は、入力波形、第２−３図は、Ｃ出力波形、第２
−４図はＤ出力波形、第３−１図は、Ｎ個入力記
憶理論メモリ。
Claims (1)
- 【実用新案登録請求の範囲】 １ Ｎ個の入力信号を１つの出力信号が記憶する
事。 ２ 出力信号を順次演算出来る事。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12357090U JPH0480148U (ja) | 1990-11-27 | 1990-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12357090U JPH0480148U (ja) | 1990-11-27 | 1990-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480148U true JPH0480148U (ja) | 1992-07-13 |
Family
ID=31871266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12357090U Pending JPH0480148U (ja) | 1990-11-27 | 1990-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480148U (ja) |
-
1990
- 1990-11-27 JP JP12357090U patent/JPH0480148U/ja active Pending
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