JPH048045A - Isdn terminal equipment - Google Patents

Abstract

PURPOSE:To recover a stop bit in real time by utilizing a pseudo stop bit and correcting a synchronizing data having a missing stop bit at the reception of a data from an ISDN. CONSTITUTION:A stop bit recovery section 2 re-inserts a pseudo stop bit resulting from number of stop bits in existing in n-set of unit data averaged by (n) to each stop bit location of the consecutive n-set of unit data including a unit data with a missing stop bit when the unit data in a synchronizing data inputted to an input section 1 is received while its stop bit is missing.

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention enables communication between multiple v series terminals that handle asynchronous data using ISDN that handles synchronous data. The present invention relates to an ISDN terminal device, and is intended to provide an ISDN terminal device that has a simple means for regenerating and recovering in real time stop bits that are missing from signals transmitted for synchronization processing.

(b) Conventional technology I SDN uses digital network to
This is a service that provides comprehensive communication of various information such as data, images, and videos via a general-purpose digital interface. It also has various features not found in conventional analog lines, such as the ability to connect various communication devices to a single interface.

However, during the development period of ISDN, terminals with V series interfaces that need to be connected to I5DX are expected to exist for a considerable period of time, so the CCITT (International Telegraph and Telephone Consultative Committee) has decided to support these terminals through ISDN. Regarding Recommendation V, 110.

Conventionally, when implementing an ISDN terminal device that supports V,110, the configuration is often based on a microcomputer, memory, etc., and the received data is temporarily recorded in memory, etc., and then stored in software. It was common to perform data conversion processing.

Here, the outline of V, 110 will be briefly explained.

An ISDN terminal device that complies with Section 2, V.110 has a bit processing unit/RAO that performs processing to remove or add stop bits to correct the clock difference between the V series terminal and the ISDN, and a bit processing unit/RAO that processes data from the terminal. To convert the speed (varies depending on the terminal) to an intermediate speed~', 11
0 frame structure (see the well-known V.110 Recommendation for details), and a second stage difference converter (RAI) that converts from an intermediate rate to an ISDN transmission rate. RA2), and on the receiving side, a second stage and a first stage difference conversion section perform inverse transformation of these second stage and first stage difference conversion units.
When the received data that is the output of the stage difference conversion unit (RA2), (RA1) and this first stage difference conversion unit does not contain the stop bit, it is supplemented to adapt to the V series terminal. Bit processing unit (RAO) that forms data
).

Incidentally, FIG. 5 shows a block diagram of a communication system including this ISDN terminal device. In the figure, P is a low speed (for example, 24
00 or 9600bps) V series terminal such as a personal computer that handles asynchronous data, K is an ISDN terminal device, N
handles high-speed (e.g. 64kbps) synchronous data.
It is SDN.

(c) Problems to be solved by the invention In conventional ISDN terminal devices, in order to reproduce the missing stop bit, data is temporarily recorded in a memory etc. as described above, and then the data is converted by software processing. However, in this case, a memory, a microcomputer, etc. are required to configure the device, which increases the scale of the device and is disadvantageous in terms of cost. In addition, with software-based processing, there is not only a problem in processing speed, but also a problem in that memory is occupied and memory usage efficiency is reduced.

The present invention has been made in view of this problem, and it is an object of the present invention to provide an ISDN terminal device that allows playback of stop bits using a device with a simple configuration, and that can also play back stop bits in real time. .

(d) Means for Solving the Problems The present invention provides a V series terminal that handles asynchronous data whose main data is a start bit, m bits (m is a positive integer) data length, and a stop bit, and the stomp pit. ISD that handles synchronous data that is added or removed as appropriate
Connect with N, ■.

I have a V series interface with a stop bit handler to support 110 compliance.
This relates to an SDN terminal device, and the stop bit processing section includes an input section for inputting synchronized data from the ISDN, and a unit data of the synchronized data inputted to the input section, in which stop bits are removed. When the n unit data is received, the n
The stomp pit reproduction section includes a stomp pit reproduction section that reinserts pseudo stop bits obtained by averaging the number of stop bits present in the unit data by n, and an output section that outputs asynchronous data from the stomp pit reproduction section. This is an ISDN terminal device characterized by the following.

(E) Operation The ISDN terminal device of the present invention has a stop bit processing section on the receiving side that processes a certain unit data of input synchronized data when the stop bit therein is removed and the unit data is received. A pseudo stop bit obtained by averaging the number of stop focuses existing in the n unit data by n is reinserted at each stop bit position of the n consecutive unit data. Then, it supplies predetermined asynchronous data to the series terminal in real time. As described above, according to the present invention, stop bits missing due to synchronization processing can be reproduced with an extremely simple configuration.

(f) Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a part (stop bit processing unit on the receiving side) of an embodiment of the ISDN terminal device of the present invention.

In the figure, 1 is an input section for inputting synchronization data from ISDN, 2 is a stop bit reproduction section, and 3 is an output section.

The input unit 1 receives synchronous data obtained by converting asynchronous data from a transmitting side V series terminal into ISDN synchronous data at a transmitting side ISDN terminal device.

Asynchronous data usually has unit data (one character) of one start bit, m bits (for example, m=8) of data, and one stop bit.

If there is no discrepancy between the clock of the ~7 series terminal on the transmitting side and the clock of the ISDN, all of the above unit data is transferred to the ISDN. However, if a deviation exists, in order to prevent malfunctions due to the deviation, processing is performed to add a stop focus to the unit data or remove a stop bit. Therefore, in the synchronization data input to the input unit 1, stop focus may be missing for certain unit data. Note that due to the nature of this shift, the period of occurrence of this dropout is sufficiently long compared to the transfer time of n pieces of unit data (n is an integer of 8 or more, 9, for example, 8).

When a certain unit data of the synchronized data input to the input unit 1 is received with the stop bit removed therein, the stop bit reproducing unit 2 reproduces each stop of n consecutive unit data including the unit data. It is configured to reinsert, at a bit position, a pseudo stop bit obtained by averaging the number of stop bits present in the n unit data by n.

Specifically, the stop bit reproducing section 2 includes a first shift register 4 having a capacity (for example, 10 bits) capable of storing at least unit data into which the received data a from the input section 1 is sequentially input; second and third shift registers 5.6 having substantially the same internal configuration as the first shift register and capable of receiving parallel transfer of data from the first shift register; and second and third shift registers 5.6; an output control section 7 that selectively outputs data from the register to the output section 3; and a monitor that monitors a start bit and a stop bit in the first shift register and provides a control signal to the output control section 7. The output section 3 is provided with a combining means 9 which receives the outputs d and g of the second and third shift registers 5 and 6 and outputs the output data i.

The monitoring means 8 includes a start bit monitoring section 10 that monitors the start bit of the first shift register 4 and a stop bit monitoring section 11 that monitors the stop bit of the first shift register 4. When the start bit monitoring unit 9 detects the start bit at the start bit position of the first shift register, the start bit monitoring unit 9 outputs data transfer signals (i, e) to
The signal is output to the bit monitoring section 11 and the output control section 7.

The stop/knob bit monitoring section 11 inspects the presence or absence of a stop bit in the first shift register 4 and supplies a control signal to the output control section 7 based on the inspection result. The output control unit 7 transfers the data transfer signal to the second shift register 5 or the third shift register 5.
A changeover switch 12 that selectively outputs to the shift register 6
and a timing control section 13 that supplies shift clocks c and f to the second and third shift registers 5.6.

The ISDN terminal device of the present invention provides high-speed (
For example, when receiving synchronized data (64 kbps), the synchronized data is transferred to the second-stage difference converter <R, A 2 > and the first-stage difference converter (RA
) is converted to low-speed data.

As mentioned above, this low-speed data includes regular unit data that has one stop bit per unit data, and invalid unit data that has stop bits added or omitted for synchronization. There is. All of these unit data are input to the stop bit reproduction section 2 through the input section 1.

The first shift register 4 sequentially receives data from the input section and shifts the data one bit at a time at the same rate as the data. As a result, there is a timing at which unit data is stored as shown in the figure.

Then, when the start focus of the input data is shifted to the final stage of the first shift register 4, the start bit detection section 10 detects the start bit and transmits a data transfer signal to the changeover switch 12 and the stop bit detection section 11. .

The data transfer signal transmitted to the changeover switch 12 is applied to the second or third shift register according to the mode of the changeover switch 12.

Furthermore, upon receiving the data transfer signal, the stop bit monitoring unit 11 immediately detects the presence or absence of a stop bit in the data. Here, if a stop bit is detected, normal operation is performed without reinserting the stop bit.

FIG. 2 is an explanatory diagram of the operation during normal operation in which regular standard data is continuously supplied to the stop bit reproduction section 2. As shown in the figure, the output of the first shift register is transferred only to the second shift register 5, and no shift register switching is performed. That is, at this time, the data transfer signal is always sent to the second shift register 5, and the shift clock, which is synchronized with the shift clock of the input data, is sent from the timing control section 13 to the second shift register.

When data is transferred from the first shift register to the second shift register, the portion excluding the stop focus (start bit and 8 data bits) is transferred, and the stop focus is added by the second shift register.

On the other hand, if the stop bit monitoring unit 11 does not detect stop focus, a stop bit reinsertion operation is performed. The operation at this time will be explained using FIGS. 3 and 4.

FIG. 3 shows a schematic diagram of the structure of the stop bit reproducing section 2 when the stop bit and I bit are reinserted. Further, FIG. 4 shows a time chart for explaining this reinsertion operation.

This time chart includes, as synchronized data input from input section 1, one regular unit data, one unit data with a missing stop bit, and seven regular unit data following this. is exemplified.

And this means that the unit data with the missing stop bit is the 1st character, and a pseudo stop bit is reinserted from the 1st character to the 8th character.
This shows that guarantee against loss of stop bits is completed in real time during the transmission period of the 8 characters, and normal operation is performed from the next unit of data.

Input data from the input section 1 (FIG. 4a) is input to the first shift register of the stop bit reproduction section 2. When the start bit ST of the unit data a1 of the first character is input to the start bit position of the first shift register 4, the start bit monitoring unit 10 outputs data transfer signals S, e.
Output.

This data transfer signal is input to the stop bit monitoring unit 1.
1 checks the stop bit position I of the first shift register 4. At this time, the stop bit monitoring unit 11 outputs a control signal to that effect since the first character unit data lacks a stop bit.

Upon receiving the data transfer signal b1, the timing control unit 13
supplies the shift clock c1 to the second shift register 5. In response to this clock, the second shift register 5 outputs the 9-bit data (1-bit start bit and 8-bit data) transferred in parallel from the first shift register 4 to the output section 3. In addition, this output section also has a 7/8 bit stop bit (
pseudo stop focus) is transferred and output. the result,
The output unit 3 outputs the first character of the asynchronous data.

This pseudo stop bit is present at each stop focus position of a total of 8 unit data (assuming n=8) after receiving the unit data missing the stop bit, and in the 8 unit data. The number of stop bits (C7 pieces) is averaged by 8, which is 7/8.

During this pseudo stop bit transfer period, in order to prevent the leading part of the next unit data from being lost, the next unit data is input to the first shift register 4 as follows:
The data is configured to be transferred in parallel not to the second shift register 5 but to the third shift register 6.

The timing control unit 13 that receives the data transfer signal e1 supplies the third shift register 6 with a shift clock f1. Third shift register 6 receiving this clock
9 is transferred in parallel from the first shift register 4
Bit data (J-bit start bit and 8-bit data) and a 7/8-bit pseudo stop bit are output to the output section 3. That is, the second character of the asynchronous data is output.

The third unit data is passed through the second shift register,
Then, the next unit data is passed through the third shift register again, and so on, and the second and third shift registers are used alternately, and a pseudo stop bit is inserted at the stop bit position of each unit data for 8 characters. .

Then, the loss of one stop bit is guaranteed by ensuring that each unit data has a pseudo stop bit at the stop bit position during the transmission period of eight unit data including that unit data, and the stop bit is The reproduced asynchronous data can be outputted from the output section 3. In this way, using the transmission time of eight unit data, the missing stop bits are replaced with pseudo stop bits to reproduce asynchronous data, thereby enabling real-time processing.

(G) Effects of the Invention As described above, according to the present invention, the I
Synchronous data with a stop bit that is missing when received from the SDN can be corrected using pseudo stop bits to become proper asynchronous data, and this correction can be performed in real time, which is useful. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a part (stomp pit processing section on the receiving side) of one embodiment of the ISDN terminal device of the present invention. FIG. 2 is an explanatory diagram of the operation during normal operation in which regular unit data is continuously supplied to the stop bit reproducing section. FIG. 3 is a schematic diagram of the structure of the stop bit reproducing section when the stop focus is reinserted. FIG. 4 is a time chart diagram for explaining this reinsertion operation. FIG. 5 is a block diagram of a communication system including this ISDN terminal device. 1 is the input section, 2 is the stop bit reproduction section, 3 is the output section,
4 is the first shift register, 5 is the second shift register, 6
1 is a third shift register, 7 is an output control section, 8 is a monitoring means, 9 is a combining means, 10 is a start bit monitoring section, 11 is a stop bit monitoring section, 12 is a changeover switch, and 13 is a timing control section.

Claims (2)

[Claims] (1) Connection between a V series terminal that handles asynchronous data whose unit data is a start bit, a data length of m bits, and a stop bit, and an ISDN that handles synchronous data in which the stop bits are added or removed as appropriate. V.
IS with V series interface with stop bit processing unit to support 110 compliance.
In the DN terminal device, the stop bit processing unit includes:
An input section for inputting synchronization data from ISDN, and when a certain unit data of the synchronization data inputted to the input section is received with the stop bit removed, consecutive n pieces ( a stop bit reproduction unit that reinserts a pseudo stop bit obtained by averaging the number of stop bits existing in the n unit data by n into each stop bit position of the unit data (n is an integer of 8 or more); , and an output section that outputs asynchronous data from the stop bit reproduction section. (2) The stop bit reproducing unit includes a first shift register having a capacity capable of storing at least unit data into which received data from the input unit is sequentially input, and an internal configuration substantially similar to that of the first shift register. second and third shift registers that are the same as the first shift register and receive parallel transfer of data from the first shift register; and an output control section that selectively outputs data from the second and third shift registers to the output section. and monitoring means for monitoring a start bit and a stop bit in the first shift register and providing a control signal to the output control section. ISDN terminal device as described.