JPH0480567B2 - - Google Patents
Info
- Publication number
- JPH0480567B2 JPH0480567B2 JP58083533A JP8353383A JPH0480567B2 JP H0480567 B2 JPH0480567 B2 JP H0480567B2 JP 58083533 A JP58083533 A JP 58083533A JP 8353383 A JP8353383 A JP 8353383A JP H0480567 B2 JPH0480567 B2 JP H0480567B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- gate
- output terminal
- high impedance
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims 5
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/52—Circuit arrangements for protecting such amplifiers
- H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子によつて構成される回路に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit made up of semiconductor elements.
通常の半導体装置の出力回路は第１図に示した
様に、VDDとVSSの間に２つのMOSトランジスタ
Q1，Q2を直列接続したもので、MOSトランジス
タQ1，Q2の夫々のゲート電極１，２には駆動信
号が夫々差動方式で入力され、出力端子３に出力
信号が出力される。 As shown in Figure 1, the output circuit of a typical semiconductor device consists of two MOS transistors between V DD and V SS .
Q 1 and Q 2 are connected in series, and drive signals are input differentially to gate electrodes 1 and 2 of MOS transistors Q 1 and Q 2 , respectively, and an output signal is output to output terminal 3. .
出力が行なわれない場合にはゲート電極１，２
の電位は、夫々とVSS間に接続されたMOSトラン
ジスタQ3，Q4と、該トランジスタQ3，Q4のゲー
トを接続した節点３に入力される高インピーダン
ス化信号φにより、接地電位とされる。従つて、
このときMOSトランジスタQ1，Q2は夫々オフ状
態にあり、出力端子３は高インピーダンス状態に
ある。出力端子が高インピーダンス状態にある期
間を利用して、この端子を他回路の入力端子とし
て共用する技術はよく知られている。さて、出力
端子が高インピーダンス状態であつて該端子を入
力端子として利用している際に、雑音やアンダー
シユート等の原因により、入力レベルが負電位と
なつた状態言いかえると出力端子３に負電位が印
加された状態を考える。現在では基板バイアス発
生回路の技術は広く知られており、通常の半導体
回路の基板は通常−２〜−4Vに逆バイアスされ
ている。したがつて−1V程度の負電位が出力端
子に印加されても、トランジスタQ1，Q2のソー
ス・ドレインである出力端子が基板電位に対して
順方向となることはない。しかし、トランジスタ
Q1，Q2のしきい電圧が0.5〜0.8V程度であれば、
ゲート電位がOVであることから、出力端子３が
−1VとなることでトランジスタQ1，Q2は出力端
子３に対してオンする。この時、トランジスタ
Q1，Q2により基板にホールの注入が行なわれ、
基板電位の上昇ひいては内部回路の誤動作をひき
おこす原因となる。この現象はアイオナイゼーシ
ヨン電流による不良として既に知られている。こ
のアイオナイゼーシヨン電流の大きさは、トラン
ジスタの電流能力に比例し、トランジスタがピン
チオフ状態にある時に最も顕著となる。従つて、
ソース・ドレイン間電圧が高い状態のトランジス
タがしきい電圧付近でオンしている時に最悪の状
態が生ずることになる。 When no output is performed, gate electrodes 1 and 2
The potential of MOS transistors Q 3 and Q 4 are connected between V SS and the high impedance signal φ that is input to node 3 connecting the gates of these transistors Q 3 and Q 4 to the ground potential. be done. Therefore,
At this time, MOS transistors Q 1 and Q 2 are each in an off state, and the output terminal 3 is in a high impedance state. A well-known technique is to utilize a period in which an output terminal is in a high impedance state to share this terminal as an input terminal for another circuit. Now, when the output terminal is in a high impedance state and the terminal is used as an input terminal, the input level becomes a negative potential due to noise, undershoot, etc. In other words, the output terminal 3 Consider a state where a negative potential is applied. At present, the technology of substrate bias generation circuits is widely known, and the substrate of a typical semiconductor circuit is normally reverse biased to -2 to -4V. Therefore, even if a negative potential of about -1V is applied to the output terminal, the output terminals, which are the sources and drains of the transistors Q 1 and Q 2 , will not be in the forward direction with respect to the substrate potential. However, the transistor
If the threshold voltage of Q 1 and Q 2 is about 0.5 to 0.8V,
Since the gate potential is OV, when the output terminal 3 becomes -1V, the transistors Q 1 and Q 2 are turned on with respect to the output terminal 3. At this time, the transistor
Holes are injected into the substrate by Q 1 and Q 2 ,
This causes an increase in the substrate potential, which in turn causes malfunction of the internal circuit. This phenomenon is already known as a defect caused by ionization current. The magnitude of this ionization current is proportional to the current capability of the transistor, and is most noticeable when the transistor is in a pinch-off state. Therefore,
The worst situation occurs when a transistor with a high source-drain voltage is turned on near the threshold voltage.
この事を第１図の出力回路にあてはめてみる
と、出力端子が負電位となつた場合、アイオナイ
ゼーシヨン電流の大部分はソース・ドレイン間電
圧の高いトランジスタQ1によつて発生している
ことになる。 Applying this to the output circuit in Figure 1, when the output terminal is at a negative potential, most of the ionization current is generated by the transistor Q1 , which has a high source-drain voltage. There will be.
本発明の目的は、出力端子に負電位が印加され
た場合に生ずるアイオナイゼーシヨン電流の発生
を防ぐ効果的な手段を提供することにある。 An object of the present invention is to provide an effective means for preventing the generation of ionization current that occurs when a negative potential is applied to the output terminal.
本発明は、基板バイアス回路を内蔵する半導体
装置において、２つのMOSトランジスタの直列
接続を主たる構成要素とする出力回路であつて、
該第１、第２のMOSトランジスタの内ドレイン
電源に近い側の第１のトランジスタのゲート端子
とソース電源との間に第３、第４のMOSトラン
ジスタを直列接続し、その第３、第４のMOSト
ランジスタの一方のゲートを出力端子に接続し、
いま一方のゲートに高いインピーダンス化信号を
入力することによつて該第１のMOSトランジス
タを高速にオフとする手段をもち、さらに該第１
のMOSトランジスタのゲート端子と出力端子間
に第５のMOSトランジスタを接続し、その第５
のMOSトランジスタのゲートをソース電源に接
続して該出力端子が高インピーダンス状態にある
時の該端子への該第１のMOSトランジスタを導
通させる方向への電圧印加に対して、該電位を該
第１のMOSトランジスタのゲートに伝達するこ
とにより、アイオナイゼーシヨン電流の発生を大
幅におさえたことを特徴とする半導体回路であ
る。 The present invention provides an output circuit whose main component is a series connection of two MOS transistors in a semiconductor device incorporating a substrate bias circuit,
Of the first and second MOS transistors, third and fourth MOS transistors are connected in series between the gate terminal of the first transistor closer to the drain power supply and the source power supply, Connect one gate of the MOS transistor to the output terminal,
The first MOS transistor has means for quickly turning off the first MOS transistor by inputting a high impedance signal to the other gate;
A fifth MOS transistor is connected between the gate terminal and the output terminal of the MOS transistor of
When the gate of the MOS transistor is connected to the source power supply and the output terminal is in a high impedance state, the voltage is applied to the terminal in a direction that makes the first MOS transistor conductive. This semiconductor circuit is characterized in that the generation of ionization current is greatly suppressed by transmitting the current to the gate of the MOS transistor No. 1.
本発明の一実施例を第２図に従つて説明する。 An embodiment of the present invention will be described with reference to FIG.
VDDとVSSの間に２つのMOSトランジスタQ1，
Q2を直列接続し、出力端子３を形成する。更に
トランジスタQ1のゲートとVSSの間に２つのMOS
トランジスタQ5，Q6を直列接続し、該トランジ
スタQ5，Q6の内一方のゲートを出力端子３に接
続し（２図ではQ6のゲート）他方のゲートを高
インピーダンス化信号φに接続する。 Two MOS transistors Q 1 between V DD and V SS ,
Connect Q 2 in series to form output terminal 3. Furthermore, two MOS transistors are connected between the gate of transistor Q1 and V SS .
Transistors Q 5 and Q 6 are connected in series, the gate of one of the transistors Q 5 and Q 6 is connected to the output terminal 3 (the gate of Q 6 in Figure 2), and the other gate is connected to the high impedance signal φ. do.
MOSトランジスタQ2のゲートとVSS間にも
MOSトランジスタQ3を接続し、該トランジスタ
Q3のゲートは高インピーダンス化信号φに接続
する。 Also between the gate of MOS transistor Q 2 and V SS
Connect MOS transistor Q3 and
The gate of Q3 is connected to the high impedance signal φ.
以上で出力端子の高インピーダンス化回路を形
成する。 With the above steps, a high impedance circuit for the output terminal is formed.
更にアイオナイゼーシヨン電流防止用トランジ
スタQ7をQ1のゲートと出力端子の間に接続し、
Q7のゲートはVSSに接続する。 Furthermore, an ionization current prevention transistor Q7 is connected between the gate of Q1 and the output terminal.
The gate of Q 7 is connected to V SS .
さて、トランジスタQ1がオンして出力端子３
が高レベルにある時トランジスタQ1のゲート１
は高レベルにある。 Now, transistor Q1 turns on and output terminal 3
gate 1 of transistor Q 1 when is at high level
is at a high level.
このときMOSトランジスタQ6はオンしてい
る。 At this time, MOS transistor Q6 is on.
高インピーダンス化信号φが入力されると、ト
ランジスタQ1のゲート電位はトランジスタQ5，
Q6を通して放電されることによりVSSレベルとな
りトランジスタQ1はすみやかにオフとなる。こ
のときトランジスタQ2もトランジスタQ3により
オフとなる。この様にして出力端子３の高インピ
ーダンス化ができる。このハイインピーダン状態
では、ゲート端子１，２は接地レベルとなつてい
る。仮りにゲート端子１にノイズ等が乗つてトラ
ンジスタＱ１の閾値よりも電位が大きくなるとト
ランジスタＱ１がオンして出力端子３の電位が上
昇するが、この時トランジスタＱ６はオンするた
め、ゲート端子１のノイズはトランジスタＱ５，
Ｑ６を介して放電されるため、トランジスタＱ１
は再びオフとなされ、出力端子はハイインピーダ
ンスとなり、上記ハイインピーダンス状態は実質
的に維持される。 When the high impedance signal φ is input, the gate potential of the transistor Q 1 changes to that of the transistor Q 5 ,
By discharging through Q 6 , the voltage becomes V SS level, and transistor Q 1 is immediately turned off. At this time, transistor Q 2 is also turned off by transistor Q 3 . In this way, the output terminal 3 can be made to have a high impedance. In this high impedance state, gate terminals 1 and 2 are at ground level. If the potential of gate terminal 1 becomes higher than the threshold of transistor Q1 due to noise, etc., transistor Q1 turns on and the potential of output terminal 3 rises. At this time, transistor Q6 turns on, so the potential of gate terminal 1 Noise is caused by transistor Q5,
Because it is discharged through Q6, transistor Q1
is turned off again, the output terminal becomes high impedance, and the high impedance state is substantially maintained.
トランジスタQ2がオンして、出力端子３が低
レベルにある時トランジスタQ1は通常オフであ
るので、出力の高インピーダンス化はトランジス
タQ3のみでできることになる。 Since transistor Q 1 is normally off when transistor Q 2 is on and output terminal 3 is at a low level, high impedance output can be achieved only by transistor Q 3 .
さて、出力端子３が高インピーダンス状態にあ
る時、出力端子３に負電位が印加されると、トラ
ンジスタQ6がオフするため、トランジスタQ1の
ゲートはVSSからきりはなされる。そしてトラン
ジスタQ7が導通することにより節点１と出力端
子３が同電位となるので、トランジスタQ1がオ
ンすることはない。 Now, when the output terminal 3 is in a high impedance state, when a negative potential is applied to the output terminal 3, the transistor Q 6 is turned off, so that the gate of the transistor Q 1 is disconnected from V SS . Since the transistor Q 7 becomes conductive, the node 1 and the output terminal 3 have the same potential, so the transistor Q 1 is not turned on.
既に示した様に、半導体装置の動作に有害なア
イオナイゼーシヨン電流の発生はソース・ドレイ
ン間電圧の高いトランジスタ（この場合トランジ
スタQ1）で起きやすいのであるが、本発明によ
り、そのトランジスタをオフのままにしておくこ
とができ、アイオナイゼーシヨン電流の発生を効
果的に防ぐことができる。 As already mentioned, ionization current, which is harmful to the operation of semiconductor devices, is likely to occur in transistors with high source-drain voltage (transistor Q 1 in this case). It can be left off, effectively preventing the generation of ionization current.
この様に本発明による回路は複雑な構成を必要
とせず、外部雑音等による誤動作を効果的に防止
できる。 As described above, the circuit according to the present invention does not require a complicated configuration and can effectively prevent malfunctions caused by external noise and the like.
これまでＮチヤンネルMOSトランジスタにつ
いて説明したがＰチヤンネルMOSトランジスタ
の場合にも、同様に適用できるのは明らかであ
る。 Although the explanation has been given so far regarding N-channel MOS transistors, it is obvious that the invention can be similarly applied to P-channel MOS transistors as well.
第１図は従来の出力回路を示す図、第２図は本
発明の一実施例の回路を示す図である。
Q1〜Q7……MOSトランジスタ。
FIG. 1 is a diagram showing a conventional output circuit, and FIG. 2 is a diagram showing a circuit according to an embodiment of the present invention. Q1 to Q7 ...MOS transistor.
Claims (1)
の電界効果トランジスタと、該第１および第２の
トランジスタの中間接続点に接続された出力端子
と、制御信号に応答して該第１のトランジスタの
ゲートを基準電位に設定する第１の手段と、該制
御信号に応答して該第２のトランジスタのゲート
を該基準電位に設定する第２の手段とを有する半
導体回路において、該第１のトランジスタのゲー
トと該出力端子との間に接続された第３の電回効
果トランジスタと、該第３の電界効果トランジス
タのゲートに基準電位を与える手段と、該第１の
手段に直列に接続された第４の電界効果トランジ
スタと、該第４の電界効果トランジスタのゲート
を該出力端子へ接続する手段とを含むことを特徴
とする半導体回路。1 first and second connected in series between power supply terminals
a field effect transistor, an output terminal connected to an intermediate junction of the first and second transistors, and first means for setting the gate of the first transistor to a reference potential in response to a control signal. , a second means for setting the gate of the second transistor to the reference potential in response to the control signal, the second means being connected between the gate of the first transistor and the output terminal. a third field effect transistor, means for applying a reference potential to the gate of the third field effect transistor, a fourth field effect transistor connected in series to the first means; and means for connecting a gate of a field effect transistor to the output terminal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58083533A JPS59208942A (en) | 1983-05-13 | 1983-05-13 | Semiconductor circuit |
| US06/609,177 US4678950A (en) | 1983-05-13 | 1984-05-11 | Output circuit having an improved protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58083533A JPS59208942A (en) | 1983-05-13 | 1983-05-13 | Semiconductor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59208942A JPS59208942A (en) | 1984-11-27 |
| JPH0480567B2 true JPH0480567B2 (en) | 1992-12-18 |
Family
ID=13805129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58083533A Granted JPS59208942A (en) | 1983-05-13 | 1983-05-13 | Semiconductor circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4678950A (en) |
| JP (1) | JPS59208942A (en) |
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| JPH01267985A (en) * | 1988-04-20 | 1989-10-25 | Fuji Photo Film Co Ltd | Driver circuit for heat emitting resistance |
| EP0369048A1 (en) * | 1988-11-15 | 1990-05-23 | Siemens Aktiengesellschaft | Circuit arrangement for regulating the load current in a power MOSFET |
| US5055711A (en) * | 1989-02-21 | 1991-10-08 | Linear Technology Corporation | Impedance control circuit for an integrated circuit node |
| US4963766A (en) * | 1989-06-28 | 1990-10-16 | Digital Equipment Corporation | Low-voltage CMOS output buffer |
| JPH03222516A (en) * | 1990-01-29 | 1991-10-01 | Fujitsu Ltd | Semiconductor device |
| US5028819A (en) * | 1990-06-08 | 1991-07-02 | Zilog, Inc. | High CMOS open-drain output buffer |
| US5160855A (en) * | 1991-06-28 | 1992-11-03 | Digital Equipment Corporation | Floating-well CMOS output driver |
| US5208719A (en) * | 1991-08-20 | 1993-05-04 | Vlsi Technology, Inc. | Output pad electrostatic discharge protection circuit for mos devices |
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| JP2508968B2 (en) * | 1993-05-25 | 1996-06-19 | 日本電気株式会社 | Semiconductor device |
| US5513140A (en) * | 1994-06-01 | 1996-04-30 | Micron Technology, Inc. | Data output buffer |
| KR0124141B1 (en) * | 1994-12-29 | 1998-10-01 | 김광호 | Data output buffer circuit for semiconductor |
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| US5844425A (en) * | 1996-07-19 | 1998-12-01 | Quality Semiconductor, Inc. | CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations |
| US5917689A (en) * | 1996-09-12 | 1999-06-29 | Analog Devices, Inc. | General purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS integrated circuits |
| US5838146A (en) * | 1996-11-12 | 1998-11-17 | Analog Devices, Inc. | Method and apparatus for providing ESD/EOS protection for IC power supply pins |
| KR100259070B1 (en) * | 1997-04-07 | 2000-06-15 | 김영환 | Data output buffer circuit |
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| US7839208B2 (en) * | 2007-12-28 | 2010-11-23 | Infineon Technologies Ag | Integrated circuit and method for operating |
| DE102017219551A1 (en) * | 2017-11-03 | 2019-05-09 | Continental Teves Ag & Co. Ohg | Polarity reversal protection arrangement, method for operating the Verpolschutzanordnung and corresponding use |
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| US3792292A (en) * | 1972-06-16 | 1974-02-12 | Nat Semiconductor Corp | Three-state logic circuit |
| JPS58207718A (en) * | 1982-05-28 | 1983-12-03 | Nec Corp | Output circuit |
-
1983
- 1983-05-13 JP JP58083533A patent/JPS59208942A/en active Granted
-
1984
- 1984-05-11 US US06/609,177 patent/US4678950A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59208942A (en) | 1984-11-27 |
| US4678950A (en) | 1987-07-07 |
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