JPH0480921A - Semiconductor manufacturing method - Google Patents

Abstract

PURPOSE:To restrain the dispersion in the etching size for equalizing the element characteristics in and between chips by a method wherein an objective layer is twice etched away so as to offset the loading effect of the dry-etching process. CONSTITUTION:A silicon nitride film 2 is deposited on the surface of a silicon oxide film 1 and then the resist patterns of a negative type resist 4 are formed on the film 2. Next, the silicon nitride film 2 is dry-etched away using fluorine base gas while the negative resist patterns are released and then the rugged surface of the film 2 is thickly coated with a positive type resist 3 so as to flatten the surface thereof 3 (e) next, the whole surface of the resist 3 is dry- etched away so that the positive type resist 3 may be left in the trench parts of the silicon nitride film 2 using oxygen and fluorine base gas. (f) Next, the oxygen/fluorine gas ratio is lowered not to excessively etch away the positive type resist 3 but to completely dry-etch away the silicon nitride film 3 and fianally, (g) the positive type resist is released to finish the patterning process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a patterning method using dry etching during a semiconductor manufacturing process.

[Conventional technology]

Currently, the films etched by dry etching include silicon oxide Ni1 (Si02), silicon nitride film (3ix
Ny), polycrystalline silicon Ill (P olySi
), aluminum (A1), etc.

FIG. 1 is a sectional view of a main part of an IC chip showing an example of patterning a silicon nitride film 2 on a silicon oxide film 1.

Symbol 3 indicates a positive resist.

A positive resist 3 is patterned on the silicon nitride film 2 (FIG. 1(a)), the silicon nitride film 2 is dry-etched (FIG. 1(b)), and the positive resist 3 is peeled off (first step). (Figure (C)), At this time, due to the loading effect of dry etching (coarse pattern areas are etched more than dense patterns), the etching dimensions of dense pattern areas are wider than those of coarse patterns in the IC chip. (le>1+ in FIG. 1(c)), resulting in dimensional variation within the chip.

[Problem to be solved by the invention]

However, the above-mentioned dimensional variations cause variations in the capabilities and characteristics of the elements within the IC chip, and when these variations exceed a certain range, they not only reduce the reliability of the IC chip, but also lead to failures when determining the overall capability or characteristics of the chip. Could be a chip.

In particular, this tendency becomes more pronounced as miniaturization progresses.

Now, as a method of suppressing this variation in etching dimensions within a chip, it is possible to use a mask or reticle that takes into account the variation in dimensions within a chip. However, it is a function to linearly change the dimensions within a mask or reticle to accommodate the variations. It is also conceivable that a dummy pattern is placed adjacent to a coarse pattern portion to change it to a dense pattern. However, even if it is possible to deal with macroscopic differences in density (for example, between the periphery of an IC chip and the inside of a cell), if the difference becomes small, there will be a limit to what can be done. Another option is to use only wet etching, which has no loading effect, but the advantage of dry etching is anisotropic etching (
The etching speed differs depending on the direction. ) is indispensable in the increasingly miniaturized IC manufacturing process, so this method is also useful.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate variations in etching methods within a chip even when dry etching with a loading effect is performed using existing masks and reticles.

[Means to solve the problem]

For this reason, in the present invention, in a patterning process using dry etching during the semiconductor manufacturing process, a resist is patterned on a layer to be etched which has been formed thicker than a predetermined thickness in advance, contrary to the usual method, and the layer to be etched is patterned to a predetermined thickness. The etching process is characterized in that a groove is formed in the layer to be etched, and after the resist is removed, the resist is applied again and the entire surface of the resist is etched so that the resist remains only in the groove of the layer to be etched, thereby completely etching the layer to be etched. .

[Effect]

According to the above method of the present invention, the layer to be etched is etched twice, but the patterns etched in the first and second times are completely opposite, and the loading effect is different from that in the first and second times.
It will conflict with the second time and cancel it out. As a result, variations in etching dimensions within the chip can be suppressed.

〔Example〕

Figure 2 is an IC diagram showing the process flow in an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the main parts inside the chip. Symbol 1 represents a silicon oxide film, 2 represents a silicon nitride film, 3 represents a positive resist, and 4 represents a negative resist.

In the embodiment shown in Fig. 2, the first etching (Fig. 2 (d)
)) is not etched at all (L1+ or L-
12) is finely finished due to the loading effect in the coarse part of the pattern (L-1a is shown relative to L-II), but this part is etched for the second time (Fig. 2 (h)).
Since this changes to the etched part (corresponding to li), the loading effect works to thicken the area, canceling out the first loading effect.

Here, since the loading effect of dry etching is canceled out as a result, variations in etching size within the chip can be suppressed. Furthermore, since dry etching is basically anisotropic, it is more effective with fine patterns, and can be performed using existing masks and reticles.

FIG. 2(a) shows silane (S) on the surface of the silicon oxide film 1.
iHa), ammonia (NHs), hydrogen (He), 90
The silicon nitride film 2 is made by plasma CVD at 0°C or below (if the film thickness in the conventional method is 150 OA, it is twice that).
It is a figure where 00A was deposited. A negative resist 4 is applied onto the silicon nitride film 2, exposed to light, and developed to form a resist pattern (Fig. 2(b)). Here, a negative resist whose photosensitive areas become insoluble in the developer was used. The above-mentioned prior art (Figure 1) uses a positive resist in which the photosensitive area is soluble in a developer as an example of use, and the first resist pattern of the present invention must be the exact opposite of the resist pattern of the prior art. In the zero-order plasma,
The silicon nitride film 2 was deposited at 1500 nm using a fluorine (F)-based gas.
Perform dry etching (Figure 2 (C)), peel off the negative resist 4 (Figure 2 (d)), apply positive resist 3 (in this case, negative resist may be used since patterning is not performed), Since the purpose of the next dry etching is to ensure that the positive resist 3 remains in the groove part (corresponding to parts 11 or 12 in FIG. 2(d)) of the silicon nitride film 2, the surface of the positive resist 3 during coating is Apply it thickly to about 2,000 to 3,000 people so that it is evenly distributed (Figure 2 (e)
), dry etching the entire surface of the positive resist 3 using oxygen (O2) and fluorine (F) based gas in plasma to leave the positive resist 3 only in the grooves of the silicon nitride film (see Figure 2 ( f)) Next, the silicon nitride film 2 was etched in the plasma by reducing the 8(02)/fluorine (F) gas ratio so that the positive resist was not etched too much.
completely dry etched (Fig. 2 (g)),
The positive resist is peeled off and the patterning is completed as shown in FIG. 2(h).

Note that the present invention is applicable not only to the loading effect caused by the pattern density relationship, but also to the suppression of etching variations within the wafer surface that the dry etching apparatus itself has. Furthermore, since it does not depend on the type of film, it can be applied to a wide variety of dry etching applications.

〔Effect of the invention〕

As described above, the present invention has the effect of suppressing etching size variations in conventional masks and reticles and making device characteristics uniform within a chip and between chips in order to offset the loading effect of dry etching.

[Brief explanation of drawings]

FIGS. 1(a) to 1(c) are cross-sectional views of a pattern portion within an IC chip showing the flow of a patterning process using dry etching in a conventional semiconductor manufacturing process, and FIGS. 2(a) to 2(c) are
(h) is a sectional view of a pattern part in an IC chip showing an embodiment of the present invention. 1...Silicon oxide film 2...Silicon nitride 1f: M 3...Positive resist 4...Negative resist or higher ] 72 Me 2 Akira (1) 夥 2 (b) 庬 2 (O) Hani 2 times/d)

Claims (1)

[Claims] Resist is patterned on the layer to be etched, which has been formed thicker than a predetermined thickness, in the opposite way to the usual method, the layer to be etched is etched to a predetermined thickness, a groove is formed in the layer to be etched, and after the resist is removed, the resist is applied again. A method for manufacturing a semiconductor, comprising etching the entire surface of the resist so that the resist remains only in the groove portion of the layer to be etched, thereby completely etching the layer to be etched.