JPH0480954A - Manufacture of bicmos integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention provides a semiconductor substrate with an N-type buried layer and a P-type buried layer. Complementary type M
The present invention relates to a method of manufacturing a BiCMOS integrated circuit device forming O8 transistors and bipolar transistors.

[Prior Art] In a BiCMOS integrated circuit device, a bipolar transistor with excellent high-frequency characteristics and a 0MO8 transistor with low power consumption are formed on the same semiconductor substrate without impairing their respective characteristics.

In addition, when manufacturing a BiCMOS integrated circuit device with
In order to shorten the manufacturing time, the bipolar transistor and the 0MO8 transistor are formed in the same process.

FIGS. 3(a) to 3(c) are cross-sectional views showing a conventional method for manufacturing a BiCMOS integrated circuit device in order of steps.

First, as shown in FIG. 3(a), a P-type silicon substrate 1 is
N-type buried layers 2a, 2b and P-type buried layer 3a on the surface of
+ 3 b + 3 c are selectively formed so as to be alternately arranged. Next, an N-type epitaxial layer 4 is formed on the entire surface.
grow. At this time, impurities diffuse into the N-type epitaxial layer 4 from each buried layer. Next, by selectively implanting P type impurities such as boron into the N type epitaxial layer 4, P type wells 5a to 5c are formed on the P type buried layers 3a to 3C, respectively. Next, after forming a silicon oxide film (not shown) on the entire surface, a silicon nitride film (not shown) is patterned on the silicon oxide film. Channel stopper regions 8 are selectively formed on the surfaces of P-type wells 5a to 5C by implanting P-type impurities such as boron ions into the entire surface using the silicon nitride film as a mask. Next, after patterning the silicon nitride film, selective oxidation is performed using the silicon nitride film as a mask to selectively form a field insulating film 6 over the entire surface, thereby isolating device regions. In this case, the N-type epitaxial layer 4a directly above the N-type buried layer 2a becomes a bipolar transistor formation region, and its surface is separated by the field insulating film 6 into a collector formation region and a base/emitter formation region. There is. Furthermore, the N-type epitaxial layer 4b and the P layer immediately above the N-type buried layer 2b are
The P-type well 5C in the area directly above the type buried layer 3c has a P-channel MO8 transistor formation area and an N-channel M-type well 5C, respectively.
This will be the area where the O8 transistor will be formed. Note that the nitride film and the oxide film used as masks are removed.

Next, as shown in FIG. 3(b), a silicon oxide film 9 having a film thickness of, for example, about 200 to 400 layers is formed in the above-mentioned element formation area by thermal oxidation, and then the collector formation area is oxidized. silicon film 9 and the N-channel MO
The silicon oxide film 9 in a part of the region where the 8 transistor is to be formed (the source/drain lead-out region) is selectively removed. Next, after a first polycrystalline silicon film is deposited on the entire surface, phosphorus atoms at a high concentration are implanted into the first polycrystalline silicon film. At this time, a phosphorus diffusion region 20 is formed on the surface of the N-type epitaxial layer 4a in the collector formation region, and a P-type well 5C in the source/drain lead-out region.
A phosphorus diffusion region 21 is formed on the surface. Thereafter, by selectively etching the first polycrystalline silicon film, the collector electrode 10a1, the gate electrode 10b*10c, and the source/drain lead wiring 10d are etched in predetermined areas.
form a pattern.

Next, as shown in FIG. 3(C), N-type impurities such as arsenic ions are selectively implanted into the P-type well 5c.
Source/drain regions 11 are selectively formed on the surface. This source/drain region 11 is formed in self-alignment with the gate electrode 10c and connected to the phosphorus diffusion region 21. Next, by selectively implanting P-type impurities such as boron ions, a graft base region 13 is selectively formed on the surface of the N-type epitaxial layer 4a, and
Source/drain regions 12 are selectively formed on the surface of type epitaxial layer 4b. This source O drain region 1
2 is formed in self-alignment with the gate electrode 10b. Next, an intrinsic base region 14 connected to the graft base region 13 is formed on the surface of the N-type epitaxial layer 4a by implanting a low concentration P-type impurity such as boron ions.

Next, after coating the glabellar insulating film 15 on the entire surface, openings are selectively formed in the interlayer insulating film 15 on the intrinsic base region 14. Next, after a second polycrystalline silicon film is deposited on the entire surface, a high concentration of N-type impurity is implanted into the second polycrystalline silicon film to form an emitter on the surface of the intrinsic base region 14 in the opening. A region 17 is formed. after that,
An emitter electrode 18 is formed on the emitter region 17 by selectively etching the second polycrystalline silicon film. Next, after depositing an interlayer insulating film 23 on the entire surface,
Openings are selectively formed in this interlayer insulating film 23. Thereafter, a low conductivity metal film made of aluminum or the like is deposited on the entire surface, and this metal film is selectively etched to form the source/drain regions 11 and 1 through the openings.
2. Form an electrode 19 connected to the graft base region 13 and the collector electrode 10a.

In this way, bipolar transistor and 0MO8
By forming transistors in the same process, BiC
The manufacturing period for MOS integrated circuit devices is shortened.

Further, the collector electrode 10a1 and the gate electrode 10b.

10c and the first wire which becomes the source/drain lead wiring 10c.
The following objectives have been achieved by implanting highly concentrated phosphorus atoms into the polycrystalline silicon film.

(2) Reduce wiring resistance of gate electrodes 10b and 10c.

(2) A phosphorus diffusion region 21 is formed to reduce the connection resistance between the source spring/drain region 11 of the N-channel MOS transistor and the source/drain lead wiring 10c.

(2) Forming a phosphorus diffusion region 20 to reduce the collector resistance of the bipolar transistor.

In particular, in the collector region of the bipolar transistor, the phosphorus diffusion region 20 is formed deeply by increasing the concentration of impurities such as phosphorus atoms implanted into the first polycrystalline silicon film, and the N-type buried layer 2a and the phosphorus diffusion region 20 are preferably interconnected. In this case, the collector resistance of the bipolar transistor can be significantly reduced.

[Problems to be Solved by the Invention] However, in the above-described conventional method for manufacturing a BiCMOS integrated circuit device, since the bipolar transistor and the 0MO8 transistor are formed in the same process, when the phosphorus diffusion region 20 is formed deeply, the phosphorus diffusion region 21 is also formed deeply, and the phosphorus diffusion region 21 and the P-type buried layer 3C are connected to each other. This poses a problem in that the withstand voltage between the source/drain region 11 of the N-channel MO8 transistor and the P-type silicon substrate 1 decreases, and the manufacturing yield of the BiCMOS integrated circuit device decreases.

On the other hand, when the phosphorus diffusion region 21 is formed shallowly, the phosphorus diffusion region 20 is also formed shallowly, and the N-type buried layer 2a and the phosphorus diffusion region 20 are not connected to each other. In this case, since the collector resistance increases, the operating speed of the bipolar transistor decreases, and the advantages of the NBICMO8 integrated circuit device are lost.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a BiCMOS integrated circuit device that can prevent a decrease in breakdown voltage of a MOS transistor and increase the operating speed of a bipolar transistor.

[Means for Solving the Problems] A method for manufacturing a BiCMOS integrated circuit device according to the present invention includes:
A first buried layer is selectively implanted into a region where a bipolar transistor is to be formed on the surface of the semiconductor substrate by implanting a second conductivity type impurity into the surface of the first conductivity type semiconductor substrate using the first mask material as a mask. and implanting a first conductivity type impurity into the surface of the semiconductor substrate using a second mask material as a mask, thereby increasing the M of the surface of the semiconductor substrate.
In the method for manufacturing a BiCMOS integrated circuit device, the method includes the steps of selectively forming a second buried layer in a region where an OS transistor is to be formed, and growing an epitaxial layer over the entire surface, wherein the second mask material It is characterized by having an opening in a portion of the first buried layer excluding a predetermined region including a region where a collector is to be formed.

[Function] In the present invention, the second mask material has an opening on the first buried layer except for a predetermined region including the region where the collector is to be formed. Therefore, when impurities of the first conductivity type are implanted into the entire surface using the second mask material as a mask,
A second buried layer is selectively formed in a region where a MOS transistor is to be formed on the surface of the semiconductor substrate, and a first conductivity type impurity is implanted into the first buried layer in a portion excluding the predetermined region. . As a result, the second conductivity type impurity is offset by the first conductivity type impurity, so that the concentration of the second conductivity type impurity in the first buried layer except for the predetermined region is substantially reduced. . Therefore, when the epitaxial layer is grown over the entire surface, the impurity in the first buried layer is diffused into the epitaxial layer to a greater extent in the predetermined region than in the portion other than the predetermined region.

Therefore, according to the present invention, the first buried layer selectively thickens (spreads) only in a predetermined region including the collector formation region toward the surface of the epitaxial layer, so that the surface of the epitaxial layer is Collector resistance can be sufficiently reduced even if the depth of the collector diffusion region formed in the region where the collector is to be formed is made shallower than in the past.This makes it possible to increase the operating speed of the bipolar transistor. On the other hand, in the manufacturing process of the BiCMOS integrated circuit device, the source/drain lead-out regions formed at the same time as the collector diffusion region can also be formed relatively shallowly, so that the withstand voltage of the MOS transistor can be prevented from decreasing.

Thereby, the manufacturing yield of BiCMOS integrated circuit devices can be improved.

Further, in the present invention, since the pattern of the mask material used when implanting the first conductivity type impurity is simply made different from the conventional one, there is no need to provide any special process.

In the present invention, it is preferable that the predetermined region includes a region where an intrinsic base is to be formed. In this case, a predetermined region of the first buried layer including the region where the collector is to be formed and the region where the intrinsic base is to be formed selectively widens toward the surface of the epitaxial layer.

Therefore, the first conductivity type intrinsic base region formed on the surface of the epitaxial layer is the second conductive type of the first buried layer.
Due to the influence of conductivity type impurities, it can be formed shallower than in the past. Thereby, the operating speed of the bipolar transistor can be further increased.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIGS. 1A to 1C are cross-sectional views showing a method for manufacturing a BiCMOS integrated circuit device according to a first embodiment of the present invention in order of steps. Note that in FIGS. 1(a) to (C), the same parts as in FIGS. 3(a) to (C) are designated by the same reference numerals, and detailed explanations of those portions will be omitted.

First, a photoresist film is patterned on a P-type silicon substrate 1, and then a high concentration of N-type impurities is selectively applied to the surface of the P-type silicon substrate 1 using this photoresist film (first mask material) as a mask. Implant ions. After removing the photoresist film, for example, 1,000 to 1
By heating the P-type silicon substrate 1 at a temperature of 200° C., the N-type impurity is activated and diffused into the P-type silicon substrate 1. As a result, as shown in FIG. 1(a), the impurity concentration is, for example, 1019 to 10"c-3 in the bipolar transistor formation region and the P channel MO8 transistor formation region on the surface of the P-type silicon substrate 1, respectively. and the junction depth is, for example, 2 to 4 μm.
N-type buried layers 2a and 2b (first buried layers) are selectively formed. Next, a mask material 24 (second mask material) made of a photoresist film having openings in the region immediately above the portion of the N-type buried layer 2a excluding the region where the collector is to be formed and in the region where the P-type buried layer is to be formed. A pattern is formed on a P-type silicon substrate 1. Next, using this mask material 24 as a mask, P-type impurities such as boron are ion-implanted into the entire surface.

After removing the mask material 24, the P-type silicon substrate 1 is heat-treated at a temperature of, for example, 300 to 1000° C., thereby activating the P-type impurity and diffusing it into the P-type silicon substrate 1.

As a result, as shown in FIG. 1(b), the impurity concentration on the surface of the P-type silicon substrate 1 is, for example, 5×10” to 5×10”.
P-type buried layers 3a, 3b*3c, which are X1018c section-3 and have a junction depth of, for example, 0.5 to 1.5 μm, are selectively formed. In addition, since P-type impurities are implanted into the N-type buried layer 2a in a portion other than the region where the collector is to be formed, the N-type impurities are canceled out by the P-type impurities, so that the N-type impurities in this portion are The concentration is substantially reduced, for example from 5 XIO'' to 5 XIO18c-3.

Next, as shown in FIG. 1(b), after removing the thermal oxide film formed in the aforementioned heat treatment step to expose the surface of the P-type silicon substrate 1,
An N-type epitaxial layer 4 is grown over the entire surface at a temperature of .degree. At this time, since the N-type epitaxial layer 4 is grown at a high temperature exceeding about 1050° C., the impurity implanted into each buried layer is diffused into the N-type epitaxial layer 4. In this case, the N-type buried layer 2a has a higher impurity concentration in the region where the collector is to be formed than the other parts, so the region where the collector is to be formed is an N-type epitaxial layer compared to the other part. It spreads widely within 4.

Thereafter, as shown in FIG. 1(C), a BiCMOS integrated circuit device can be manufactured by the same steps as the conventional method shown in FIGS. 3(a) to 3(C). In this case, in this embodiment, even if the phosphorus diffusion region 20.21 is formed shallowly, the phosphorus diffusion region 20.21 connected to the collector electrode 10a
0 is securely connected to the N-type buried layer 2a.

According to this embodiment, even if the phosphorus diffusion region 20 formed in the collector region is formed relatively shallowly, the N-type buried layer 2a and the phosphorus diffusion region 20 are connected to each other, so that the collector resistance can be sufficiently reduced. The operating speed of the bipolar transistor can be sufficiently increased. On the other hand, since the phosphorus diffusion region 21 formed in the source/drain lead-out region can also be formed relatively shallowly, the P-type buried layer 3c and the phosphorus diffusion region 21 are not connected to each other. Therefore, it is possible to prevent the withstand voltage of the N-channel MO8 transistor from decreasing. Therefore, the manufacturing yield of BicMO8 integrated circuit devices can be improved.

In addition, in this embodiment, the excellent effects described above can be obtained without any special process simply by making the pattern of the mask material 24 different from the conventional pattern.

FIGS. 2(a) to 2(C) are cross-sectional views showing a method for manufacturing a BiCMOS integrated circuit device according to a second embodiment of the present invention in order of steps. In Fig. 2 (a) to (C), the same parts as in Fig. 1 (a) to (C) and Fig. 3 (a) to (C) are given the same reference numerals, and the details of the parts are indicated. Explanation will be omitted.

First, as shown in FIG. 2(a), a P-type silicon substrate 1 is
After selectively forming N-type buried layers 2a and 2b on the surface, an oxide film is formed on P-type silicon substrate 1 by vapor phase growth. Next, by selectively removing the oxide film, the region directly above the N-type buried layer 2a, excluding the region where the collector is to be formed and the region where the intrinsic base is to be formed, is removed.
A mask material 25 having openings in the region immediately above b and in the region where the P-type buried layer is to be formed is patterned. Note that the oxide film slightly remains on the entire surface of this mask material 25. Next, P-type impurities are added to the entire surface using the mask material 25 as a mask, thereby selectively forming P-type buried layers 3a* 3b and 3c on the surface of the P-type silicon substrate 1. Also, N
The graft base formation area portion of the mold buried layer 2a and N
P-type impurities are implanted into the type buried layer 2a, and the N-type impurities are canceled out by the P-type impurities, so that the concentration of the N-type impurities in these portions is substantially reduced.

Next, as shown in FIG. 2(b), a P-type silicon substrate 1
After exposing the surface of , an N-type epitaxial layer 4 is formed on the entire surface.
grow. At this time, the impurity implanted into each buried layer diffuses into the N-type epitaxial layer 4. In this case, N
The type buried layer 2a widely spreads in the N-type epitaxial layer 4 because the impurity concentration in the collector formation region and the intrinsic base formation region is higher than in the graft base formation region. In addition, the N-type buried layer 2
Since the concentration of N-type impurities in b is reduced, the spread to the N-type epitaxial layer 4 is smaller than in the first embodiment.

After sowing, a BiCMOS integrated circuit device can be manufactured in the same manner as in the first embodiment, as shown in FIG. 2(C).

According to this embodiment, even if the phosphorus diffusion regions 20 and 21 are formed relatively shallowly, the N-type buried layer 2 and the phosphorus diffusion region 2o are connected to each other in the same manner as in the first embodiment. Therefore, the operating speed of the bipolar transistor can be sufficiently increased, and the withstand voltage of the N-channel MO8 transistor can be prevented from decreasing.

Furthermore, in this embodiment, the N-type buried layer 2a also forms the N-type epitaxial layer 4 in the region immediately below the intrinsic base region 14.
It spreads widely toward the surface of a. Therefore, since the surface concentration of the N-type epitaxial layer 4a increases, the P-type intrinsic base region 14 can be formed shallower than before. This also has the effect of further increasing the operating speed of the bipolar transistor.

[Effects of the Invention] As explained above, according to the present invention, the second conductivity type
Since the first conductivity type impurity is added to a predetermined portion of the second conductivity type first buried layer when forming the buried layer, the first conductivity type impurity is added to a predetermined region including the collector formation region. The portion extends into the epitaxial layer to a greater extent than the portion outside of the epitaxial layer. Therefore, even if the depth of the collector diffusion region formed on the surface of the epitaxial layer in the subsequent process is made shallower than in the past, the frefter resistance can be sufficiently reduced.
It is possible to increase the operating speed of bipolar transistors. On the other hand, since the source/drain lead-out region formed at the same time as the collector diffusion region can be made relatively shallow, it is possible to prevent the withstand voltage of the MOS transistor from decreasing. Thereby, the manufacturing yield of BiCMOS integrated circuit devices can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are cross-sectional views showing the manufacturing method of a BiCMOS integrated circuit device according to the first embodiment of the present invention in order of steps, and FIGS. 3(a) to 3(c) are cross-sectional views showing the manufacturing method of the BjCMO3 integrated circuit device according to the second embodiment in the order of steps, and FIGS.
1A and 1B are cross-sectional views showing a method for manufacturing an OS integrated circuit device in order of steps. 1; P-type silicon substrate, 2 a + 2 b: N-type buried layer, 3a+ 3b, 3c: P-type buried layer, 4+4a+
4b; N-type epitaxial layer; 5; P-type well; 8; field insulating film; 8; channel stopper region; 9; silicon oxide film; 10a; collector electrode; 10b, 10c;
Gate electrode, 10d; source/drain lead wiring, 11
, 12; source fist drain region, 13; graft base region, 14; intrinsic base region, 15, 23; interlayer insulating film, 17; emitter region, 18; emitter electrode, 19; electrode, 20. 21; phosphorus diffusion region, 24, 25; Mask material

Claims (2)

[Claims] (1) A first buried layer is formed in a region where a bipolar transistor is to be formed on the surface of the semiconductor substrate by implanting a second conductivity type impurity into the surface of the first conductivity type semiconductor substrate using the first mask material as a mask. selectively forming a second
The first mask material is applied to the surface of the semiconductor substrate using the mask material as a mask.
A BiCMOS integrated circuit device comprising the steps of: selectively forming a second buried layer in a region where a MOS transistor is to be formed on the surface of the semiconductor substrate by implanting a conductivity type impurity; and growing an epitaxial layer over the entire surface. BiCMOS manufacturing method, wherein the second mask material has an opening in a portion of the first buried layer excluding a predetermined region including a region where a collector is to be formed.
A method of manufacturing an integrated circuit device. (2) The method for manufacturing a BiCMOS integrated circuit device according to claim 1, wherein the predetermined region includes a region where an intrinsic base is to be formed.