JPH0481006A - Level detection circuit - Google Patents

Abstract

PURPOSE:To obtain a direct current level following up the amplitude fluctuation of a signal to be inputted by providing a high-pass filter which is connected to the drain of a third FET and transmits an output signal. CONSTITUTION:An MESFET 2 is provided while connecting the source to the source of an MESFET 1, and an MESFET 3 is provided while inputting an inverted phase signal, which phase is inverted to that of a regular phase signal, at the gate, connecting the drain to the drain of the MESFET 2 and connecting the source to the source of the MESFET 2. Then, the first order high-pass filter is provided while being composed of a resistor 13 and a capacitor 14 so as to be connected to the drain of the MESFET 3 and to output the output signal. Further, an MESFET 4 is provided while connecting the gate to a current supply reference power source 10, connecting the source to a power source 8 and connecting the drain to the source of the MESFET 1. Thus, the level detection circuit composed of the MESFET 1-4 can be obtained to detect the level change of the input signal and to transmit a signal close to the direct current level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level detection circuit configured with MESFETs that detects level changes in an input signal and sends out a signal close to a DC level.

[Conventional technology]

Conventionally, this type of level detection circuit, as shown in FIG.
A signal is supplied to the input terminal 25 on one side of the differential input amplifier 21 so that the output of the differential input amplifier 21 can be obtained at the gate of the FET 22, and the drain of the FET 22 is connected to the power supply.
The source of FET 22 is connected to the capacitor 23, and the drain of FET 24 is connected to the remaining input terminal of the differential input amplifier 21, and the source of FET 24 is grounded.
A bias is supplied to the reference potential input terminal 26 connected to the gate of the capacitor 23, and a so-called peak value holding operation is performed in which charge is accumulated in the capacitor 23 according to the level of the input signal.

[Problem to be solved by the invention]

The conventional level detection circuit described above is configured to store charge in a capacitor and hold the peak value of the input signal level, so the capacitance value of the capacitor cannot be built into a single integrated circuit board and is determined by external components. This has the drawback of increasing the number of external parts. In addition, the matching of the capacitor's charging time and discharging time changes the respective time constants to FETs.
Since it is determined by excessive bias, it is difficult to set, and it has the disadvantage that it is unsuitable for sufficient retention and detection with good response. In other words, if the retention characteristics are improved, the discharge time becomes longer and the level change response time becomes longer. Conversely, if the level change response time is shortened, the retention characteristics are sacrificed. ing.

[Means to solve the problem]

The level detection circuit of the present invention includes a first FET whose gate is connected to a reference potential, whose drain is connected to a first power supply via a first resistor, and whose source is connected to a second power supply; A second FET receives a phase signal, has a drain connected to the first power supply via a second resistor, and a source connected to the source of the first FET, and a gate that has a reverse phase to the positive phase signal. A third FET whose drain is connected to the drain of the second FET and whose source is in contact with the source of the second FET is connected to the drain of the third FET to output a signal. It is configured to include a high-frequency cutoff filter for sending out.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2(a)
2 is a diagram showing an example of the waveforms of positive-phase and negative-phase input signals.
Figure (b) is a diagram showing an example of the waveform of the output signal of the drain of MESFET 2.3, Figure 2 (C) is a diagram showing an example of the output waveform, and Figure 3 is a diagram showing an example of the output waveform of the high-frequency cutoff filter in this example. FIG. 3 is a diagram showing an example of frequency characteristics.

In FIG. 1, this embodiment is a MESF with a gate connected to a reference potential 9, a drain connected to a power supply 7 via a charge resistor 5, and a source connected to the drain of a power supply MESFET 4.
ETI, a MESFE72 whose gate inputs a normal phase signal, whose drain is connected to the power supply 7 through a load resistor 6, and whose source is connected to the source of the MESFETI, and whose gate inputs a negative phase signal that is opposite to the positive phase signal. input and drain is MESF
MESFET3 whose source is connected to the drain of ET2 and whose source is connected to the source of MESFET2, a primary high-frequency cutoff filter consisting of a resistor 13 and a capacitor 13 that output an output signal connected to the drain of MESFET3, and whose gate is a current source reference power supply. 10 is connected and the source is connected to the power supply 8 and the drain is connected to the source of MESFETI.
4.

Next, regarding the operation of this embodiment, FIG. 1, FIG. 2(a),
This will be explained using (b), (C) and FIG.

Signals a and b having the complementary relationship shown in FIG. 2(a) are input to complementary signal input terminals 11 and 12 in FIG. 1! At this time, an arbitrary reference potential is applied to the gate of MESFET I. As a result, a waveform A shown in FIG. 2 appears at node 16 in FIG.

This shows that the half-wave current of one signal is replaced by a full-wave rectification function by inputting a complementary signal.

If the waveforms of signals a and b shown in FIG. 2(a) change to signals c and d with increased signal amplitudes, the waveform appearing at node 16 in FIG. 2 will be the waveform of FIG. 2(b). As shown in C, there is a response in which the maximum level of the waveform is maintained and the amplitude increases downward.

FIG. 2(c) shows the waveform A of FIG. 2(b) at the output terminal 15.
, C shows the transition of the DC level. E and F in Figure 2(c)
correspond to waveforms A and C in FIG. 2, respectively.

Each level in FIG. 2(c) is the level appearing at the output terminal 15 in FIG. 1. This is provided via a high-cut filter having the characteristics shown in FIG.

In Fig. 3, when this high-pass cutoff filter is set to the first order, fl indicates the signal frequency, f2 indicates the cutoff frequency, and the attenuation amount is sufficient at the frequency of fl, for example, -60 dB.
In order to obtain this value, f2 must be set 3 decades lower. Therefore, the amplitude of waveform C in Fig. 2(b) is 1010
When set to 0O, F in FIG. 2(C) becomes a level compressed to 1 mV, resulting in a signal almost at a DC level.

〔Effect of the invention〕

As explained above, in the present invention, the gate is connected to the reference potential, the drain is connected to the first power source via the first resistor,
A first FET whose source is connected to the second power supply, and a second FET whose gate inputs a positive phase signal, whose drain is connected to the first power supply via a second resistor, and whose source is connected to the source of the first FET. 2 FET, and a third FE whose gate inputs a negative phase signal that is opposite in phase to the positive phase signal, whose drain is connected to the drain of the second FET, and whose source is connected to the source of the second FET.
By configuring the FET to include a T and a high-frequency cutoff filter that is connected to the drain of the third FET and sends out an output signal, it is possible to obtain a DC level that follows the amplitude fluctuations of the input signal. . Furthermore, when dealing with ultrahigh-speed signals specific to compound semiconductor devices, even if the order of the high-frequency cutoff filter is 1st, the resistor and capacitor can be easily built into the integrated circuit, making it unnecessary to attach them externally.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2(a)
2 is a diagram showing an example of the waveforms of positive-phase and negative-phase input signals.
Figure (b) is a diagram showing an example of the waveform of the output signal of the drain of MESFET 2.3, Figure 2 (c) is a diagram showing an example of the output waveform, and Figure 3 is a diagram showing an example of the output waveform of the high-frequency cutoff filter in this example. FIG. 4 is a diagram showing an example of frequency characteristics. FIG. 4 is a circuit diagram showing an example of a conventional level detection circuit. 1.2, 3.4... MESFET, 5, 6... Load resistance, 7.8... Power supply, 9... Reference power supply, 10...
・Current source reference power supply, 11.12...Complementary signal input terminal, 13.14...1st-order high-frequency cutoff filter, 15.-
・Pressure terminal, 21...Differential input amplifier, 22.24・
...FET, 23...Capacitor, 25...Signal input terminal, 26...Reference potential input terminal, 27...Power supply.

Claims (1)

[Claims] A first FET has a gate connected to a reference potential, a drain connected to a first power supply via a first resistor, and a source connected to a second power supply; a second FET connected to the first power supply through a resistor of 2 and having a source connected to the source of the first FET;
a third FET whose gate inputs a negative phase signal opposite to the normal phase signal, whose drain is connected to the drain of the second FET, and whose source is in contact with the source of the second FET; A level detection circuit comprising: a high-frequency cutoff filter connected to the drain of an FET to send out an output signal.