JPH0481052U - - Google Patents

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Publication number
JPH0481052U
JPH0481052U JP12434590U JP12434590U JPH0481052U JP H0481052 U JPH0481052 U JP H0481052U JP 12434590 U JP12434590 U JP 12434590U JP 12434590 U JP12434590 U JP 12434590U JP H0481052 U JPH0481052 U JP H0481052U
Authority
JP
Japan
Prior art keywords
substrate
silicon
field effect
ion sensor
insulated gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12434590U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12434590U priority Critical patent/JPH0481052U/ja
Publication of JPH0481052U publication Critical patent/JPH0481052U/ja
Pending legal-status Critical Current

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  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例斜視図、第2図
は第1図のa−a′部を示す図、第3図、第4図
、第5図は本考案の第2、第3、第4の実施例を
示す図、第6図はフローセルを示す図、第7図は
本考案の評価システムを示す図、第8図は本考案
の効果を表わす図である。 1……シリコン基板、2……第2のシリコン基
板、3……穴、4……電極、5……イオン感応膜
、6……ソース、7……ドレイン、8……二酸化
シリコン、9……窒化シリコン、10……二酸化
シリコン膜、11,12……ウエル、13……プ
リント基板、14,15……電界効果トランジス
タ、16……ガラス基板、17……空間、18…
…集積化イオンセンサ、19……ピン、20……
ワイヤ、21……入口側流路、22……出口側流
路、23……アクリルブロツク、24……エポシ
キ樹脂、25……フローセル、26……ポンプ、
27……バルブ、28……試料ボトル、29……
参照電極、30……参照電極用ボトル、31……
廃液ボトル、32,33……演算増幅器、34,
35……定電流源、36……抵抗、37……出力
、38……記録計。
Fig. 1 is a perspective view of the first embodiment of the present invention, Fig. 2 is a view taken along the line a-a' in Fig. 1, and Figs. FIG. 6 is a diagram showing the flow cell, FIG. 7 is a diagram showing the evaluation system of the present invention, and FIG. 8 is a diagram showing the effects of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Second silicon substrate, 3... Hole, 4... Electrode, 5... Ion sensitive film, 6... Source, 7... Drain, 8... Silicon dioxide, 9... ... silicon nitride, 10 ... silicon dioxide film, 11, 12 ... well, 13 ... printed circuit board, 14, 15 ... field effect transistor, 16 ... glass substrate, 17 ... space, 18 ...
...Integrated ion sensor, 19...Pin, 20...
Wire, 21... Inlet side channel, 22... Outlet side channel, 23... Acrylic block, 24... Epoxy resin, 25... Flow cell, 26... Pump,
27... Valve, 28... Sample bottle, 29...
Reference electrode, 30... Reference electrode bottle, 31...
Waste liquid bottle, 32, 33... operational amplifier, 34,
35... Constant current source, 36... Resistor, 37... Output, 38... Recorder.

Claims (1)

【実用新案登録請求の範囲】 1 基板に1個又は複数個の絶縁ゲート電界効果
トランジスタを設け、該絶縁ゲート電界効果トラ
ンジスタのゲート部及び電極部以外の表面に、該
絶縁ゲート電界効果トランジスタのゲート部及び
電極部に対応した部分に、表面と裏面とで面積が
異なる穴のあいた第2の平板を設け、該穴の中に
イオン感応膜を形成したことを特徴とする集積化
イオンセンサ。 2 請求項第1項に記載の絶縁ゲート電界効果ト
ランジスタは、二酸化シリコン(SiO)の上
に窒化シリンコン(Si)又は酸化アルミ
ニウム(Al)又は酸化タンタル(Ta
)を積層した二層ゲート絶縁膜を有すること
を特徴とする集積化イオンセンサ。 3 請求項第1項に記載の平板は、シリコン又は
ガラス又はポリイミド等の高分子から成り、フオ
トリソグラフイー技術とエツチング技術により穴
が設けられたことを特徴とする集積化イオンセン
サ。 4 請求項第1項に記載のイオン感応膜はポリ塩
化ビニル、可塑剤、イオン感応物質から成ること
を特徴とする集積化イオンセンサ。 5 請求項第1項に記載の基板は、シリコン基板
、シリコン・オン・サフアイア(SOS)基板、
アモルフアスシリコン基板等の半導体基板、又は
プリント基板、ガラス基板、エポキシ基板等の絶
縁基板であることを特徴とする集積化イオンセン
サ。
[Claims for Utility Model Registration] 1. One or more insulated gate field effect transistors are provided on a substrate, and the gate of the insulated gate field effect transistor is provided on the surface other than the gate part and electrode part of the insulated gate field effect transistor. An integrated ion sensor characterized in that a second flat plate is provided with holes having different areas on the front and back surfaces in a portion corresponding to the electrode portion and the electrode portion, and an ion-sensitive membrane is formed in the hole. 2. The insulated gate field effect transistor according to claim 1 comprises silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), or tantalum oxide (Ta 2 ) on silicon dioxide (SiO 2 ) .
An integrated ion sensor characterized by having a two-layer gate insulating film laminated with O 5 ). 3. An integrated ion sensor according to claim 1, wherein the flat plate is made of silicon, glass, or a polymer such as polyimide, and has holes formed therein by photolithography and etching techniques. 4. An integrated ion sensor, wherein the ion-sensitive membrane according to claim 1 comprises polyvinyl chloride, a plasticizer, and an ion-sensitive substance. 5. The substrate according to claim 1 is a silicon substrate, a silicon-on-sapphire (SOS) substrate,
An integrated ion sensor characterized by being a semiconductor substrate such as an amorphous silicon substrate, or an insulating substrate such as a printed circuit board, glass substrate, or epoxy substrate.
JP12434590U 1990-11-28 1990-11-28 Pending JPH0481052U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12434590U JPH0481052U (en) 1990-11-28 1990-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12434590U JPH0481052U (en) 1990-11-28 1990-11-28

Publications (1)

Publication Number Publication Date
JPH0481052U true JPH0481052U (en) 1992-07-15

Family

ID=31872003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12434590U Pending JPH0481052U (en) 1990-11-28 1990-11-28

Country Status (1)

Country Link
JP (1) JPH0481052U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009545723A (en) * 2006-06-30 2009-12-24 インテル・コーポレーション Three-dimensional integrated circuit for analyte detection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009545723A (en) * 2006-06-30 2009-12-24 インテル・コーポレーション Three-dimensional integrated circuit for analyte detection

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