JPH0481109A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To realize a differential amplifier circuit with a high voltage utility by driving a differential amplifier circuit composed of P-channel MOS transistors(TRs) and a differential amplifier circuit composed of N-channel MOS TRs in parallel. CONSTITUTION:When an input whose level is 4.1V or over being a power supply voltage is given to a differential amplifier composed of P-channel TRs Q1, Q2, the differential amplifier is not active. However, the input level activates a differential amplifier composed of N-channel TRs Q8, Q9. On the other hand, when an input whose level is 0.9V or below being a GND level is given to the differential amplifier composed of N-channel TRs Q8, Q9, the differential amplifier is not active. However, the input level activates a differential amplifier composed of P-channel TRs Q1, Q2. When an input whose level stays between 0.9V-4.1V being an intermediate level is given to both the differential amplifiers composed of the P-channel TRs Q1, Q2 and the N-channel TRs Q8, Q9, they are active and the differential amplifier circuit is operated while the current of them is synthesized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit that can operate with input voltage being activated widely between a power supply voltage direction and a ground direction.

[Conventional technology]

3 and 4, conventionally (used)
An example of a differential amplifier circuit configured with C-MOS is shown. In the figure, Q, Q2 are P-channel MOS transistors constituting a differential amplifier, and each gate electrode serves as one input circuit and one input circuit of the differential amplifier circuit. Q
3. Q, is a current mirror circuit composed of N-channel MOS transistors, Q, is a transistor Q, ,Q,
A P-channel transistor for a constant current source that supplies a bias current to the part to which the source of Q6 is connected, and Q6 is a diode-connected P-channel MOS transistor.
A current is set by resistor R7 to bias transistor Q.

Next, the operation will be explained. A differential circuit in which the source electrodes of P-channel MOS transistors Q, , Q, are connected together functions as a differential amplifier circuit by inputting each gate electrode of the transistors Q, , Q. In other words, the transistors Q, ,Q
The drain current of transistor Q2 changes, and this current flows through transistor Q
The signal is amplified using a current mirror circuit consisting of Q3 and Q4 as a load, and the signal is output to the output terminal. Note that this circuit is a well-known circuit that has been commonly used in various fields and whose configuration and operation are well known.

[Problem to be solved by the invention]

The conventional type differential circuit described in FIG. 3 has the disadvantage that the operable voltage range of the input voltage is limited due to the bias voltage required for the N-channel or P-channel transistors of which it is constructed. For example, if the power supply voltage of these differential amplifier circuits is the standard voltage (=5V) of commonly used digital devices, the input side cannot necessarily operate with the full amplitude between 0■ and 5■. , the operable range is limited by the loss voltage.

Figure 4 illustrates the DC bias state of the circuit in Figure 3,
explain. In this case, the GND (ground) direction is VGs of Q3 and ■ of Q+. 5. Q, ■. The operating limit voltage VIL is determined by , V IL =V Gg3+ V DSI V GSI
Therefore, Vcsz =VGSl =0. 8V,
When Vns=Q9IV (operates up to), VIL=O68V+O, IV-0, 8V=O, IV.

On the other hand, the power supply V side is Vos of Q5, Q, or Q2
is determined by the VGS of V +H−V cc (V o
s, V cs+), and Voss =0. IV, VGSI =0.
8 V, V+u-5(0,8±0.1)-4
, IV.

This means that the circuit in Figure 3 is 0.1 in the GND (ground) direction.
The loss voltage is about 2, whereas VCC (PI is 0.
A loss voltage as large as 9V occurs, and even if a voltage of 5V is applied, the actual input voltage is V ((on the side, 4.1
This indicates that there is a restriction that only up to ■ can be entered.

Here, ■. , = 0.8V is an example of the gate/dose ○N voltage necessary for biasing the transistors used in differential amplification, and ①. s-0
, IV is the threshold voltage at which the drain-source voltage operates as a transistor.

Next, FIG. 5 shows a circuit in which the P type and N type in FIG. 3 are all inverted to have opposite polarity structures. In this case, as shown in FIG. 6, the circuit becomes a circuit in which the loss voltage on the GND grounding side is greatly limited, contrary to the circuit shown in FIG. This is Vcc
This can be clearly seen from the asymmetry of the output waveform when inputting a sine wave centered on /2 (=2.5V).

Conventional circuits have the drawback that no matter which method is used, a large loss voltage is always generated on the ground or power supply side, and the input operating range is narrowly limited.

This invention was made to solve the above problems, and the operating input voltage range of the differential amplifier circuit is set to GND.
It is an object of the present invention to provide a differential amplifier circuit with a high voltage utilization rate that is sufficiently low on both the (ground) side and the C side.

Another object of the present invention is to solve the problem of large VGS voltage loss peculiar to C-MO3, which is often a problem in C-MOS analog circuits, and to improve its performance.

[Means to solve the problem]

The present invention was made in order to solve these problems, and in order to widen the input voltage of the differential amplifier circuit, it consists of a differential amplifier circuit composed of a P-channel MO3I-transistor and an N-channel MO3 transistor. The characteristics were improved by driving differential amplifier circuits in parallel.

[Effect]

According to the present invention, the loss operation region on the power supply side, which is disadvantageous in the P-channel MO3) transistor configuration, is covered by the differential amplifier circuit of N-channel operation, and the loss operation area on the GND (ground) side, which is disadvantageous in the N-channel MO3) transistor configuration, is covered. P voltage overhead
The purpose of the improvement is to expand the operating range over the entire range from CND to VCC by covering it with a differential amplifier circuit of channel MOS transistors.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a differential amplifier circuit according to an embodiment of the present invention,
In the figure, Q, , Q2 are P-channel MO3 transistors constituting a differential amplifier, and their output drain currents are transmitted to N-channel MO3 transistors Q, , Q, and further connected to transistors Q3 and Q + 7. set,
A pair of current mirror circuits is configured by transistors Q4 and Ql.

On the other hand, the output drain current of the differential amplifier composed of N-channel MOS transistors Q8 and Q9 is transmitted to P-channel MOS transistors Q1° and Q1□, as in the case of the P-channel, and is further transmitted to transistors Q1° and Qll. One set of current mirror circuits is composed of one set of transistors Q, □, and Q13. Also, transistors Q1□ and Ql. , the drains of transistors Q18 and Ql3 are connected to each other.

Note that the transistor Q6. The part consisting of Q6 and resistor R7 and transistors Q + 4 and Q +
5 and resistor R16 is a bias circuit similar to that shown in the conventional circuit.

Next, the operation of this embodiment will be explained.

In FIG. 1, in the region of 4.1 square or more near the power supply, the differential amplifier inputting the Pch transistor consisting of Q, . . . Q2 does not operate, as in the conventional example. However, Nc
h) Transistor Q,,Q.

The differential amplifier operates when the input is . transistor Q
8 drain current I. 8 is a transistor Q.

I O1+ is caused to flow by the current mirror circuit of Q. This I Dll flows into transistor Q4, and IDl11 flows through a current mirror circuit consisting of transistors Q, , Q, . At this time transistor Q1
and Q2 are inoperable, so I nI, I D2
does not flow. In other words, in this case, the differential circuit consisting of Q, , Q, which is disadvantageous for operation in the direction of the power source, will be in the so-called OFF mode if the human power is 4.1 mm or more, and the drain of transistor Q2 will not be connected to Q4 of the current mirror circuit. However, it is cut off, and the current mirror element of transistor Q4 is activated in the direction of the t source.
, Q, 0 The output current of the Nch differential circuit is transmitted from Qll to operate.

On the other hand, in the region of 0.9V or less near GND, the differential amplifier that inputs the Nch transistor consisting of transistors Q, , Q, does not operate, as in the conventional example. but,
A differential amplifier that receives Pch transistors Q, , Q2 as inputs operates.

The drain current ID2 of the transistor Q2 is Q, ,Ql,
l018 flows through the current mirror circuit.

At this time, transistors Q, ,Q, are inoperable, so
■. 8.11 will not be broadcast. In other words, in this case GN
The differential amplifier consisting of Q, , Q, which is disadvantageous for operation in the D direction, becomes OFF mode with an input of 0.9V or less, and the transistor Q, although connected to Q I G of the current mirror circuit, is cut off. P-channel transistor Q, which is off and activated in the GND direction.
It will operate only with the output current of the differential amplifier that inputs Q2.

In the intermediate range of 0.9V to 4.1V, the differential amplifiers of both P-channel transistors Q, , Q2 and N-channel transistors Q, , Q operate, and these currents are combined. Operate.

As described above, the present embodiment uses a differential amplifier 10. A differential amplifier consisting of Nch and P-channel transistors. ,,.

This is a differential amplifier circuit that outputs the sum of the respective currents and has a common input.

Hereinafter, other embodiments of the present invention will be described with reference to the drawings.

In FIG. 2, Q and Q2 are differential amplifiers composed of P-channel MOS transistors, and the drains of both transistors are transistor Q.

Connected to a current mirror circuit consisting of Q4.

On the other hand, in the differential amplifier composed of N-channel MO3) transistors Q, , Q, the output drain current is transmitted to transistors Q lo , Ql 3, one set is made up of transistors Q1°, Ql, transistors Q, 3 . Q
, 2 constitute one set of current mirror circuits.

In order to calculate the sum of the output drain currents of these differential amplifiers, the drains of transistors Q1□ and Q, and Q and Q4 are connected to each other, thereby achieving the same effect as the embodiment shown in FIG. .

Further, in the above embodiment, the case of a CMO3) transistor was explained, but it goes without saying that the same effect can be obtained even if a bipolar transistor is used. However, when considering base current, field effect transistors are more advantageous.

5. Effects of the Invention] As described above, according to the present invention, P channel MO3)
By driving the differential amplifier circuit composed of transistors and the differential amplifier circuit composed of N-channel MO3 in parallel to improve their characteristics, the operating input voltage range of the differential amplifier circuit can be increased. VC also on CND (ground) side
It is possible to obtain a differential amplifier circuit with a high voltage utilization rate that extends sufficiently to the C side, and also has ■GS!, which is unique to CMOS transistors, which is often a problem in CMOS analog circuits. This has the effect of solving the problem of large pressure loss and improving performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a differential amplifier circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing another embodiment of the invention, and FIG. 3 is a diagram showing the configuration of a conventional differential amplifier circuit. 4 are explanatory diagrams illustrating the bias voltage of FIG. 3, and FIGS. 5 and 6 are explanatory diagrams illustrating other embodiments of the present invention and their bias voltages. FIG. 7 is a diagram showing the basic block configuration of the present invention. In the figure, Ql, Q-, Qs, Q6. QloQ I
I+ Qtz, Qti are Pch transistors, Q3
゜Q,,Q,,Q,,Q,,,Q,, are Nch transistors, and Rt, Rt- are resistors. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The source electrodes of the first and second P-channel field effect transistors are made common, a signal is inputted to the first and second gate electrodes, and the drain electrodes of the first and second transistors are inputted to the first and second gate electrodes. A first differential amplifier circuit configured by connecting a required number of current mirror circuits, and a common source electrode of the third and fourth N-channel field effect transistors, and a common source electrode of the third and fourth N-channel field effect transistors. a second differential amplifier circuit configured by inputting a signal and connecting a required number of current mirror circuits to the drain electrodes of the third and fourth transistors; The circuits are operated simultaneously, and the current output signals output from the current mirror circuits connected to the respective drains of the first differential amplifier circuit and the second differential amplifier circuit are combined and output. differential amplifier circuit.