JPH0481128A - A/d converter - Google Patents

Abstract

PURPOSE:To realize the A/D converter with high accuracy by sampling and holding a 1st reference voltage comparatively higher and a 2nd reference voltage comparatively lower generated from a reference voltage generating circuit in response to a clock signal generated by a clock signal generating circuit. CONSTITUTION:Since a 2nd sample-and-hold circuit 201 and a 3rd sample-and- hold circuit 202 have the same characteristic as that of a 1st sample-and-hold circuit 21, the fluctuation of the output of the 2nd sample-and-hold circuit 201 and the 3rd sample-and-hold circuit 202 due to a droop of the output is the same as the fluctuation due to droop of the output of the 1st sample-and-hold circuit 21. Thus, a high level reference voltage 203 and a low level reference voltage 204 of a low-order A/D converter circuit 51 are respectively shifted by the same quantity as a shift VE at a time t3 of the output of a subtractor amplifier 4. As a result, the low-order A/D converter circuit 51 outputs a correct digital quantity not including any error.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an A/D converter.

[Conventional technology]

FIG. 3 shows, for example, "l5SCC'88 DIGEST
224 of “OF TECIINICAL PAPERS”
It is a block diagram showing the conventional A/D converter shown in page,
This is an example of a 10-bit A/D converter. In addition, for ease of explanation, a functional block level configuration diagram is shown. In the figure, thick solid lines indicate analog signal lines, and thin solid lines indicate digital signal lines. is the output of sample hold circuit 2 as A
32 and 33 are the high-potential side reference voltage application terminals and low-potential side reference voltage application terminals of the upper A/D conversion circuit 3, and 34 is the upper A/D conversion circuit. 6-bit D/A converting intermediate output 31 of circuit 3
A conversion circuit, 36 is the bias terminal of the D/A conversion circuit 34, 35 is the output of the upper A/D conversion circuit 3, and 4 is the terminal between the output of the sample hold circuit 2 and the output of the D/A conversion circuit 34. A subtraction amplifier that performs subtraction; 51 is a 6-bit lower A/D conversion circuit that A/D converts the output of the subtraction amplifier 4;
2 and 53 are the high potential side reference voltage application terminal and low potential side reference voltage application terminal of the lower A/D conversion circuit 51, 54 is the output of the lower A/D conversion circuit 5], and 6 is the upper A/D conversion circuit 3.
7 is an output latch that stores the output of the adder 6, and 8 is an output terminal.

Furthermore, 9 is a pressure generation circuit connected to the 1
A reference voltage generation circuit 11 is connected to a high potential side reference voltage application terminal 52 and a low potential side reference voltage application terminal 53 of the conversion circuit 51, and 11 is a clock signal generation circuit, CLI, CL.
2 and CL3 are the outputs of the clock signal generation circuit 11 that drives the sample hold circuit 2, the upper A/D conversion circuit 3, and the lower A/D conversion circuit 51, respectively.

Next, the operation of the conventional example will be explained. When the clock signal CLI is at L level, the output of the sample and hold circuit 2 follows the analog signal input from the input terminal 1. Next, when the clock signal CL changes to the H level, the output node j of the sample and hold circuit 2 is held at the voltage value of the analog signal input from the input terminal 1 at this moment. Then, at the same time as or after entering the holding state, this holding voltage is subjected to A/D conversion corresponding to the upper A/D conversion circuit 3 or the upper 6 bits 7). This timing is controlled by clock signal CL2. The conversion range of the upper A/D conversion circuit 3 is determined by the voltages applied to the high potential side reference voltage application terminal 32 and the low potential side reference voltage application terminal 33 of the upper A/D conversion circuit 3, respectively. That is, a voltage smaller than the high-potential side reference voltage and larger than the low-potential side reference voltage is converted into a 6-bit digital value.

On the other hand, the intermediate conversion result 3 of the upper A/D conversion circuit 3 is
The signal is input manually to the A conversion circuit 34 and subjected to D/A conversion. D/A
The conversion range of the conversion circuit 34 is controlled by the voltage applied to the output terminal 36. That is, the bias voltage generation circuit 9 matches the conversion ranges of the upper A/D conversion circuit 3 and the D/A conversion circuit 34 via the bias terminal 36. As a result, an analog signal corresponding to the quantization level of the output digital value of the upper 6-viso hA/D conversion circuit 3 is obtained. This analog signal is sent to the upper A/D converter circuit 3.
There is only a resolution corresponding to , that is, a resolution of 6 bits.

Therefore, by subtracting and amplifying the output value of the D/A conversion circuit 34 from the manually input analog value using the subtraction amplifier 4, components finer than 6 bits included in the input analog value are extracted and amplified.

FIG. 4 shows an example of the above operation, in which the input analog signal, the output value of the D/A conversion circuit 34, and the subtracting amplifier 4
The output values of are shown by dotted lines, dashed lines, and solid lines, respectively. Further, the voltage axis is expressed by the output value of the upper A/D conversion circuit 3 corresponding to the voltage. In addition, in the present invention, A/
It is assumed that the human analog signal changes rapidly compared to the D conversion speed, that is, the discontinuity on the time axis due to the operation of the sample and hold circuit 2 is sufficiently small.
Further, the amplification factor of the subtraction amplifier 4 is set to 1.

Next, the lower A/D conversion circuit 51 A/D converts the output of the subtraction amplifier 4. This timing is clock signal CL3.
controlled by Further, assuming that the minimum value of the ideal output of the subtracting amplifier 4 is vFl and the maximum value is VF2, the upper limit of the conversion range of the lower A/D conversion circuit 51 is VF 1 +2x (V
F2-VF 1), 'T limit is VFI-2x (VF2
-VFI). In other words, the originally required lower A/D
The upper and lower limits of the conversion range of the conversion circuit 51 are expanded (in this example, four times the original conversion range). As a result, even if the upper A/D conversion result contains some error,
If the output of the subtraction amplifier 4 is within the above conversion range, it can be corrected. Note that this correction will be explained in detail later. The digital output of the lower A/D conversion circuit 51 is set to V when the output of the subtracting amplifier 4 changes ideally.
When changing from Fl to VF2, “ooooooo”
It becomes a digital value from "001111". or,
When it is smaller than VFI, it becomes a negative number, and when it is larger than VF2, it becomes a digital value larger than "001111'. Note that the upper and lower limits of the conversion range of the lower A/D conversion circuit 51 as described above are determined by the reference voltage generation circuit 10. It is controlled by the voltage generated by the

The output 35 of the upper A/D conversion circuit 3 and the output 54 of the lower A/D conversion circuit 51 are added by the adder 6 to form a 10-bit digital quantity, which is output digitally via the output latch 7 and the output terminal 8. . However, since the output 35 of the upper A/D conversion circuit 3 represents the upper 6 bits, for example, if the upper result is "IO old/old", it is shifted to the upper 4 digits and becomes "1.001010000°". , is added to the output 54 of the lower A/D conversion circuit 51. In this way, by adding the output 35 of the upper A/D conversion circuit 3 and the output 54 of the lower A/D conversion circuit 51, the upper A/D conversion circuit 3 is added to the output 54 of the lower A/D conversion circuit 51. D
Even if the output 35 of the conversion circuit 3 contains some error, it can be corrected. This is widely known as digital correction, and the principle thereof will be explained below.

Now, input analog quantity or exactly digital quantity (DC + DF
). However, DC is a digital amount corresponding to the output 35 of the upper A/D conversion circuit 3, and DF is a digital amount corresponding to the output 54 of the lower A/D conversion circuit 51. For example, (DC+DF) or “10010111
01', DC is "100101000" in binary notation.
0” D F becomes “1101”. Digital quantity D
If the analog quantities for C and DF are VC and VF, the manual analog quantity VIN is V I N - VC + VF
,,(1). Here, if an error occurs in the process of upper A/D conversion and as a result, DC' is shifted by DE from the true value DC, then DC' becomes DC' - DC+DE, -(2). As a result, if the analog quantity corresponding to DE is VE, the output 35 of the upper A/D conversion circuit 3 is VC' -VC+VE ・=
(3) becomes. Now, for ease of explanation, subtracting amplifier 4
Assuming that the amplification factor of is 1, the output VSUB of the subtraction amplifier 4 is VSUB −VIN from equations (1) and (3).
-VC' -VF-VE (4). Therefore, the lower A/D conversion circuit 51 which A/D converted VSUB.
The output 54 is DF'-DF-DE (5). As a result, by adding DC' and DF', the final digital output DOUT is obtained from equations (2) and (5): DOUT = DC' + DF' - DC + DF
- (6), and the error component DE is canceled out.

[Problem to be solved by the invention]

It is known that the conventional A/D converter is configured as described above, and that droop occurs in the actual sample and hold circuit 2. That is, by changing the clock signal CLI from the L level to the H level, the output of the sample and hold circuit 2 is held at the current voltage value of the analog signal input from the input terminal 1, but this holding voltage is not ideal. Ideally, it remains constant until the next time the clock signal CLI changes to the L level, but in reality, fluctuations occur.

Due to the droop phenomenon of this sample and hold circuit 2,
The following problems were encountered.

FIG. 5 shows such a problem, which will be explained along with FIG. In FIG. 5(a), the dotted line 101 is the analog input signal, the thin solid line 102 and the thick solid line 103 are the ideal output of the sample and hold circuit 2, and the actual output caused by droop.
The dashed line]04 is the output of the D/A conversion circuit 34. In FIG. 5(b), the thin solid line 105 and the thick solid line 106, the ideal and actual outputs of the subtracting amplifier 4, the dashed lines 107 and 108
Reference voltage application terminals 52 and 5B of the lower A/D conversion circuit
is the applied voltage. Figures 5(e), (d) and (e)
) are the clock signals CL1. ．． CL2 and CL
3 timing is shown.

When the signal CL1 changes from the L level to the H level, the sample and hold circuit 2 starts holding the analog input [0]. After this, if there is no droop in the sample-and-hold circuit 2, the voltage at point A is held and becomes a thin solid line 102, or in reality, the voltage at point A fluctuates due to droop and becomes a thick solid line 103.

Next, at the moment when the clock signal CL2 changes from the L level to the H rail, the upper A/D conversion circuit 3 performs A/D conversion. At this time, the actual sample hold circuit 2
Since the output of is shifted from its ideal output B' to B, an error occurs in the process of upper A/D conversion. However, if the circuits other than the upper A/D converter circuit 3 are operating ideally, such errors will be canceled out by the digital correction described above, and no errors will appear in the final eight circuits of the A/D converter. do not have. Thereafter, the subtraction amplifier 4 subtracts the output of the D/A conversion circuit 34 from the output of the sample and hold circuit 2. However, if the output of the sample-and-hold circuit 2 is ideal, the output of the subtracting amplifier 4 will be a thin solid line 105, or actually a thick solid line 106.

Next, at the moment when the clock signal CL3 changes from L level to H level, lower A/D conversion is performed. The output of sample hold circuit 2 at this time is the ideal thin solid line 10
If it is point C' on 2, the D/A conversion circuit 34 at this time
The output of the subtraction amplifier 4 becomes a point E' on the thin solid line 105. However, in reality, a droop occurs and the output of the sample-and-hold circuit 2 is shifted from the ideal point C' by V'E to point C on the thick solid line 103, so the output of the subtracting amplifier 4 is also Point E'
It is shifted by VE from VE to point E on the thick solid line 106, and from this value, the lower A/D conversion circuit 5] converts the A/D
It will be converted.

On the other hand, the high potential side reference voltage 1 of the lower A/D conversion circuit 51 [
]7 and the low potential reference voltage 108 are fixed, so
The relationship between analog human power and digital output determined by these is also fixed. That is, the input level corresponding to each digital output is all fixed, and the lower A/D conversion circuit 5
It is designed to give the correct output when an input of 1 is ideal. Therefore, there is a problem in that an error occurs in the input of the lower A/D converter circuit 51 due to droop, and as a result, the final result of the A/D converter also causes an error.

This invention was made to solve the above-mentioned problems, and its purpose is to provide an A/D converter that can generate correct A/D conversion results without errors even if droop occurs in the sample and hold circuit. shall be.

[Means to solve the problem]

In the A/D converter according to the present invention, a first sample and hold circuit is connected to the analog input terminal, an A/D conversion circuit is connected to the first sample and hold circuit, and a second sample and hold circuit is connected to the A/D converter. A third sample and hold circuit is connected between the reference voltage generation circuit of the /D conversion circuit and the high potential side reference voltage application terminal of the A/D conversion circuit, and a third sample hold circuit is connected between the reference voltage generation circuit of the reference voltage generation circuit and the A/D conversion circuit. The first to third sample and hold circuits are connected between the low potential side reference voltage application terminals and have the same characteristics, and the first to third sample and hold circuits are connected to the same clock signal generation circuit. They are designed to be driven simultaneously by clock signals.

[Effect]

In the present invention, a second sample and hold circuit is connected between the reference voltage generation circuit of the A/D conversion circuit and the high potential side reference voltage application terminal of the A/D conversion circuit, and the reference voltage generation circuit and the A/D conversion circuit are connected to each other. The third sample and hold circuit connected between the low potential side reference voltage application terminals of the D conversion circuit has the same characteristics as the first sample and hold circuit connected to the analog input terminal, and has the same characteristics as the first sample and hold circuit connected to the analog input terminal. Since the hold circuits are driven at the same time, the high-potential side reference voltage and low-potential side reference voltage of the A/D conversion circuit are controlled by the output fluctuation due to the droop of the first sample-and-hold circuit connected to the analog input terminal. It is possible to change the amount by the same amount as the amount.

〔Example〕

FIG. 1 is a block diagram of a series-parallel type A/D converter showing one embodiment of the present invention. In the figure, 21 is a first sample and hold circuit connected to analog input terminal 1;
01 is the reference voltage generation circuit 10 and the lower A/D conversion circuit 51
A second sample-and-hold circuit 202 is connected between the high-potential side reference voltage application terminal 52 and has the same characteristics as the first sample-and-hold circuit 21; A third sample and hold circuit CL1 is connected between the low potential side reference voltage application terminals 53 of 51 and has the same characteristics as the first sample and hold circuit 21, and CL1 is a clock signal output from the clock signal generation circuit 11. This is the drive signal for the first to third sample and hold circuits 21, 201 and 202. The other configurations are the same as those of the conventional example, and their explanation will be omitted.

Next, the operation of the A/D controller configured as described above will be explained. FIG. 2 shows the operation. In FIG. 2(a), the dotted line 01 is an analog input signal, the thin solid line 02 and the thick solid line 103 are the ideal output of the first sample-and-hold circuit 21 and the actual output due to the influence of droop, and the chain line 104 is D /A conversion circuit 34 output. In addition, in FIG. 2(b), the thin solid line 05 and the thick solid line 106 are the theoretical output of the subtracting amplifier 4 and the actual output due to the influence of droop, and the chain line 2
03 is the reference voltage applied to the high potential side reference voltage application terminal 52, and the chain line 204 is the reference voltage applied to the low potential side reference voltage application terminal 53.

On the other hand, FIGS. 2(c), 2(d) and 2(e) show clock signals CL1. It shows the timing of CL2 and CL3, and shows the timing of clock signals CLI, CL2 and CL3.
are assumed to change from L level to H level at times t1, t2, and t3, respectively.

Therefore, at time t1 when the clock signal CLI changes from L level to H level, the first sample and hold circuit 21 outputs the analog input signal 101 at point A at time t1.
starts holding the voltage. After that, if there is no droop in the first sample and hold circuit 21, the voltage at point A will be held and the ideal output 102 will be obtained, but in reality, the voltage at point A will tend to decrease due to the influence of the droop, and the output will be like output 103. become.

Next, at time t2 when the clock signal CL2 changes from L level to H level, the first sample hold circuit 2
The output of 1 is subjected to upper A/D conversion by the upper A/D conversion circuit 3, and the intermediate output 31 is D/A converted by the D/A conversion circuit 34, and then sent to one input terminal of the subtracting amplifier 4. is input.

Incidentally, at time t2, the output of the first sample and hold circuit 21 is at the ideal point B' as shown in FIG. 2(a).
It has shifted from point B to point B. However, as long as circuits other than the upper A/D converter circuit 3 are operating ideally, the error generated in the upper A/D converter circuit 3 is canceled out by the digital correction described above, so the D/A Conversion circuit 34
The output may be treated as the output 104 obtained by D/A converting the output at the ideal point B' of the first sample and hold circuit 21. Therefore, the subtraction amplifier 4 subtracts the output 104 of the D/A conversion circuit 34 from the output of the first sample hold circuit 21. If the output of the first sample-and-hold circuit 21 is ideal, the output of the subtraction amplifier 4 is the thin solid line in FIG. 2(b)]0
5, or actually becomes a thick solid line 10b due to the influence of droop.

Next, at time t3 when the clock signal CL3 changes from the L level to the H level, the output of the subtracting amplifier 4]06 becomes the lower A/
A/D conversion is performed by the D conversion circuit 51. If the output of the first sample and hold circuit 21 at this time is the ideal point C', subtraction is performed with the point on the output 104 of the D/A conversion circuit 34 at time t3, and the point on the output 104 of the D/A conversion circuit 34 at time t3 is The output becomes point E' on the thin solid line 105. However, in reality, a droop occurs and the first sample and hold circuit 2
Since the output of subtraction amplifier 4 is shifted by VE from point C' on ideal output 102 to point C on output 103, the output of subtraction amplifier 4 is also shifted by VE from point E' on output 105. This results in a point E on the output 1.06, and this output value is A/D converted.

The above operation is similar to the conventional example.

On the other hand, the reference voltage generation circuit 10 and the lower A/D conversion circuit 51
The second sample hold circuit 201 connected to the high potential reference voltage application terminal 52 of the reference voltage generation circuit 10 and the low potential reference voltage application terminal 5 of the lower A/D conversion circuit 51.
The third sample and hold circuit 202 connected to
Since it is driven by the common clock signal CL with the first sample and hold circuit 21 connected to the analog input terminal 1, the output of the reference voltage generation circuit 1o starts from the same time t1 as the start of holding the analog input. (Figure 2(b)
Start holding points X and Y) at Furthermore, since the second sample and hold circuit 2[]1 and the third sample and hold circuit 202 are configured to have the same characteristics as the first sample and hold circuit 21, the second sample and hold circuit 201 The amount of variation in the output of the third sample and hold circuit 202 due to droop is the same as the amount of variation in the output of the first sample and hold circuit 21 due to droop. Therefore, the time t during which the lower A/D conversion is performed
In No. 3, the high potential side reference voltage 203 and the low potential side reference voltage 204 of the lower A/D conversion circuit 51 are respectively as follows.
Shift fiVE of the output of subtraction amplifier 4 at time t3
The voltage values at points W and Z are shifted by the same amount from their initial values X and Y. That is, the relationship between the analog input and digital output of the lower A/D conversion circuit 51, in other words, the analog input level corresponding to each digital output has also all been shifted by VE.

As a result, for the analog input of the lower A/D converter circuit 51 that includes an error due to the droop generated by the first sample and hold circuit 21, the lower A/D converter circuit 51 outputs a correct digital amount that does not include the above-mentioned error. will be output. In this way, by actively utilizing the droop generated in the sample-and-hold circuit, the error in the output of the subtracting amplifier 4 caused by the droop is corrected when lower A/D conversion is performed, and the error in the output of the A/D converter is corrected. The final result will also be correct.

In the above embodiments, the present invention is applied to a series/parallel type A/D converter, but it is also possible to apply the present invention to other types than the series/parallel type A/D converter. For example, the present invention can also be applied to parallel or cascaded A/D converters that perform A/D conversion by manually inputting the output of a sample and hold circuit connected to an analog input terminal to an A/D conversion circuit. It is.

〔Effect of the invention〕

As described above, according to the present invention, the first sample-and-hold circuit connected to the analog input terminal and the clock signal generation circuit has the same characteristics, and the reference voltage generation circuit of the A/D conversion circuit and the clock signal generation circuit have the same characteristics. By each of the second and third sample and hold circuits connected to the signal generation circuit,
A relatively high first voltage generated by the reference voltage generation circuit in response to a clock signal generated by the clock signal generation circuit.
Since the reference voltage of the reference voltage and the relatively low second reference voltage are sampled and held, even if an error occurs in the analog input of the A/D conversion circuit due to the droop of the first sample and hold circuit, the A/D conversion will not be performed. The result can be corrected when performed and produce correct A/D conversion results;
The effect can be obtained by using a highly accurate A/D converter.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an A/D converter according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an A/D converter according to an embodiment of the present invention.
Waveform diagram for explaining the operation of the converter, Figure 3 is a conventional A/D
The configuration diagrams showing the converter, FIGS. 4 and 5, are the conventional A
FIG. 3 is a waveform diagram for explaining the operation of the /D converter. In the figure, 1 is an analog input terminal, 1o is a base f$ voltage generation circuit, 11 is a clock signal generation circuit, 21 is a first sample hold circuit, 51 is an A/D conversion circuit, and 52 is a high potential side reference voltage application. Terminal 53 is a low potential side reference voltage application terminal, 201 is a second sample hold circuit, 202
is the third sample and hold circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) An analog input terminal for inputting an analog signal to be A/D converted, a clock signal generation circuit for generating a clock signal, connected to the analog input terminal and the clock signal generation circuit, and responsive to the clock signal. a first sample and hold circuit that samples and holds the analog signal; a reference voltage generation circuit that generates a first reference voltage of relatively high voltage and a second reference voltage of relatively low voltage; a second sample and hold circuit that is connected to the clock signal generation circuit, has the same characteristics as the first sample and hold circuit, and samples and holds the first reference voltage in response to the clock signal; and the reference. a third sample and hold circuit that is connected to the voltage generation circuit and the clock signal generation circuit, has the same characteristics as the first sample and hold circuit, and samples and holds the second reference voltage in response to the clock signal; and the first and second reference voltages connected to the first to third sample and hold circuits and sampled and held by the second and third sample and hold circuits as high potential side and low potential side reference voltages. An A/D converter comprising: an A/D conversion circuit that A/D converts the analog signals received at application terminals and sampled and held in the first sample and hold circuit.