JPH0481300U - - Google Patents

Info

Publication number
JPH0481300U
JPH0481300U JP12421190U JP12421190U JPH0481300U JP H0481300 U JPH0481300 U JP H0481300U JP 12421190 U JP12421190 U JP 12421190U JP 12421190 U JP12421190 U JP 12421190U JP H0481300 U JPH0481300 U JP H0481300U
Authority
JP
Japan
Prior art keywords
semiconductor memory
memory device
transistor
sense amplifier
storage section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12421190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12421190U priority Critical patent/JPH0481300U/ja
Publication of JPH0481300U publication Critical patent/JPH0481300U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は従来の回路構成を示す図、第3図は第2図の
構成の動作を説明する図、第4図および第5図は
本考案の回路の動作を説明する図である。 DEC……アドレスデコーダ、AD〜AD
……アドレスデータ、P1……プリチヤージ用P
MOSトランジスタ、N〜N……メモリ用N
MOSトランジスタ、N……デイスチヤージ用
NMOSトランジスタ、I1,I2……インバー
タ。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
This figure shows a conventional circuit configuration, FIG. 3 is a diagram explaining the operation of the configuration of FIG. 2, and FIGS. 4 and 5 are diagrams explaining the operation of the circuit of the present invention. DEC...Address decoder, AD1 to ADn
... Address data, P1 ... P for pre-charge
MOS transistor, N1 to Nn ...N for memory
MOS transistor, Nd ... NMOS transistor for discharge, I1, I2... Inverter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 直列となつたプリチヤージ用トランジスタ、n
段のメモリ用トランジスタおよびデイスクチヤー
ジ用トランジスタを含む情報記憶部及びセンスア
ンプを有し、プリチヤージを行なうことによつて
前記センスアンプより情報記憶部の情報を検出す
る半導体記憶装置において、前記センスアンプの
入力端子をデイスチヤージ用MOSトランジスタ
のドレイン側に接続したことを特徴とする半導体
記憶装置。
Pre-charge transistor in series, n
In a semiconductor memory device, the semiconductor memory device has an information storage section including a memory transistor and a disk charge transistor in a stage, and a sense amplifier, and detects information in the information storage section from the sense amplifier by performing precharging. 1. A semiconductor memory device, characterized in that an input terminal of the device is connected to a drain side of a discharge MOS transistor.
JP12421190U 1990-11-28 1990-11-28 Pending JPH0481300U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12421190U JPH0481300U (en) 1990-11-28 1990-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12421190U JPH0481300U (en) 1990-11-28 1990-11-28

Publications (1)

Publication Number Publication Date
JPH0481300U true JPH0481300U (en) 1992-07-15

Family

ID=31871871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12421190U Pending JPH0481300U (en) 1990-11-28 1990-11-28

Country Status (1)

Country Link
JP (1) JPH0481300U (en)

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