JPH0481347B2 - - Google Patents
Info
- Publication number
- JPH0481347B2 JPH0481347B2 JP58147106A JP14710683A JPH0481347B2 JP H0481347 B2 JPH0481347 B2 JP H0481347B2 JP 58147106 A JP58147106 A JP 58147106A JP 14710683 A JP14710683 A JP 14710683A JP H0481347 B2 JPH0481347 B2 JP H0481347B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate electrode
- injection
- punch
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
- H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
Landscapes
- Non-Volatile Memory (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Description
【発明の詳細な説明】
我々は従来、低プログラム電圧高集積不揮発性
メモリとしてPunch−Through注入型メモリを提
案した。第１図にそのPunch−Through注入型メ
モリの代表的な実施例の断面図を示す。Ｎ型メモ
リの場合、Ｐ型半導体基板１表面に互い分離して
各々N+型のキヤリア供給領域であるソース領域
２とキヤリア吸収領域であるドレイン領域３を設
け、ソース領域２とドレイン領域３との間のチヤ
ネル領域に第１チヤネル領域と第２チヤネル領域
を設け、第１チヤネル領域上に選択ゲーム酸化膜
７を介して選択ゲート電極５を設け、第２チヤネ
ル領域上にはゲート酸化膜６を介して浮遊ゲート
電極４を設けた構造である。浮遊ゲート電極４
は、ゲート酸化膜６を介してドレイン領域３と強
い容量結合をしており、浮遊ゲート電極４の電位
は主にドレイン領域３の電位によつて制御されて
いる。浮遊ゲート電極４の中の電子密度に依存し
てソース・ドレイン領域間のチヤネル領域のコン
ダクタンスが変化することから情報を読み出す。DETAILED DESCRIPTION OF THE INVENTION We have previously proposed a Punch-Through injection type memory as a low program voltage, highly integrated non-volatile memory. FIG. 1 shows a cross-sectional view of a typical example of the Punch-Through injection type memory. In the case of an N-type memory, a source region 2 which is an N + type carrier supply region and a drain region 3 which is a carrier absorption region are provided separately on the surface of a P-type semiconductor substrate 1, and the source region 2 and the drain region 3 are separated from each other. A first channel region and a second channel region are provided in the channel region between them, a selection gate electrode 5 is provided on the first channel region via a selection game oxide film 7, and a gate oxide film 6 is provided on the second channel region. This is a structure in which a floating gate electrode 4 is provided via a. floating gate electrode 4
has strong capacitive coupling with the drain region 3 via the gate oxide film 6, and the potential of the floating gate electrode 4 is mainly controlled by the potential of the drain region 3. Information is read from the fact that the conductance of the channel region between the source and drain regions changes depending on the electron density in the floating gate electrode 4.
情報の書込み、即ち、電子を浮遊ゲート電極４
の中へ注入するには、次に説明するPunch−
Through注入方法を用いる。 Writing information, that is, transferring electrons to the floating gate electrode 4
To inject into the Punch−
Use the through injection method.
第１図の示したソース領域２と浮遊ゲート電極
４との間の距離lPをある程度短くすると、ドレイ
ン領域３に逆バイアスを印加した場合、ソース領
域２と基板１との間の空乏層２ａと、第２チヤネ
ル領域の表面空乏層３ａとが交わり、第１チヤネ
ル領域付近に空間電荷領域を形成する。この空間
電荷領域の電位がドレイン領域３に印加された逆
バイアスの増加とともに低下し、キヤリア供給領
域であるソース領域２からキヤリア吸収領域であ
るドレイン領域３へと電子が流れる。いわゆる
Punch−Through現象が行る。第２チヤネル領域
の表面ポテンシヤルが空間電荷領域のポテンシヤ
ルに比べ約3.2ev（半導体基板１とゲート酸化膜６
との間とポテンシヤルバリア障壁の値）以上低く
なると、ソース領域２からPunch−Through現象
で流出した電子の一部は浮遊ゲート電極４へ入る
ことができる。例えば、lP＝1μｍ、基板濃度NA
がNA＝1016atoms・cm-3第２チヤネル領域の表面
ポテンシヤルが基板１に対して7v低くなると
Punch Through注入が起る。 If the distance l P between the source region 2 and the floating gate electrode 4 shown in FIG. and the surface depletion layer 3a of the second channel region intersect, forming a space charge region near the first channel region. The potential of this space charge region decreases as the reverse bias applied to the drain region 3 increases, and electrons flow from the source region 2, which is a carrier supply region, to the drain region 3, which is a carrier absorption region. So-called
The Punch-Through phenomenon takes place. The surface potential of the second channel region is approximately 3.2ev compared to the potential of the space charge region (semiconductor substrate 1 and gate oxide film 6).
When the potential barrier becomes lower than (the value between the potential barrier and the barrier value), some of the electrons flowing out from the source region 2 due to the Punch-Through phenomenon can enter the floating gate electrode 4. For example, l P = 1 μm, substrate concentration N A
is N A = 10 16 atoms cm -3 when the surface potential of the second channel region is 7v lower than that of the substrate 1.
Punch Through injection occurs.
上記のように我々が提案した構造のPunch
Through注入型メモリは、注入が浮遊ゲート電
極４のソース領域側の先端で主に行なわれるこ
と、さらに、Punch Through方向と注入方向が
異なることにより電子注入効率が低くプログラム
電圧の低電圧化をリミツトしていた。 Punch of our proposed structure as above
In the through injection type memory, the injection is mainly performed at the tip of the floating gate electrode 4 on the source region side, and furthermore, because the punch through direction and the injection direction are different, the electron injection efficiency is low and it limits the reduction of the programming voltage. Was.
本発明は、上記のような従来のPunch
Through注入型メモリの欠点を克服したもので
あり、注入効率の高いPunch Through注入型の
半導体不揮発性メモリを提供するものである。 The present invention is based on the conventional Punch as described above.
This overcomes the drawbacks of through injection type memory and provides a punch through injection type semiconductor nonvolatile memory with high injection efficiency.
本発明に関連するPunch−Through注入型メモ
リの参考例について第２図から第４図を用いて詳
細に説明する。 A reference example of a Punch-Through injection type memory related to the present invention will be explained in detail with reference to FIGS. 2 to 4.
第２図は、本発明の半導体不揮発性メモリに関
連する第１の参考例の断面図である。まず構造に
ついて説明する。Ｎ型半導体不揮発性メモリの場
合について説明する。段差が形成されているＰ型
半導体基板１１に、段差領域を介してキヤリア供
給領域であるソース領域１２と、キヤリア吸収領
域であるドレイン領域１３を設け、段差領域とド
レイン領域１３にまたがつて酸化膜１６を介して
浮遊ゲート電極１４を設ける。第２図の本発明に
関連する第１の参考例の場合、浮遊ゲート電極１
４の電位はドレイン領域１３の電圧で制御できる
ように浮遊ゲート電極１４とドレイン領域１３と
強い容量結合を形成している。 FIG. 2 is a sectional view of a first reference example related to the semiconductor nonvolatile memory of the present invention. First, the structure will be explained. The case of an N-type semiconductor nonvolatile memory will be explained. A source region 12 which is a carrier supply region and a drain region 13 which is a carrier absorption region are provided on a P-type semiconductor substrate 11 in which a step is formed via the step region, and oxidation is performed across the step region and the drain region 13. A floating gate electrode 14 is provided through the film 16. In the case of the first reference example related to the present invention shown in FIG.
4 forms a strong capacitive coupling between the floating gate electrode 14 and the drain region 13 so that the potential of the drain region 13 can be controlled by the voltage of the drain region 13.
第１の参考例の情報の読み出しは、浮遊ゲート
電極１４の中の電子密度によつて、ソース・ドレ
イン領域間のパンチスルー電圧が異なることによ
り読み出される。 Information in the first reference example is read by changing the punch-through voltage between the source and drain regions depending on the electron density in the floating gate electrode 14.
次の情報の書込み、即ち、浮遊ゲート電極１４
への電子注入は、ソース・ドレイン領域間で
Punch Throughをおこすことにより行う。
Punch Through注入のおこる電圧をドレイン領
域１３に印加する必要がある。ドレイン領域１３
に逆バイアスを印加することにより浮遊ゲート電
極１４に接した注入領域に空乏層１３ａが形成さ
れる。ソース領域１２の空乏層１２ａと注入領域
の空乏層１３ａが重なると、ソース領域１２と注
入領域との間の空間電荷形成領域に空間電荷領域
が形成されPunch Throughが起こる。 Writing the next information, i.e. floating gate electrode 14
electron injection into the source and drain regions.
This is done by causing Punch Through.
It is necessary to apply a voltage to the drain region 13 at which Punch Through injection occurs. drain region 13
By applying a reverse bias to , a depletion layer 13a is formed in the implanted region in contact with the floating gate electrode 14. When the depletion layer 12a of the source region 12 and the depletion layer 13a of the injection region overlap, a space charge region is formed in the space charge formation region between the source region 12 and the injection region, and punch through occurs.
Punch Through注入の起こる条件は、ソース
領域１２と基板１１との間にバイアスが印加され
ていない場合、次のように表わすことができる。 The conditions for Punch Through implantation to occur, when no bias is applied between the source region 12 and the substrate 11, can be expressed as follows.
VA／lp・WpΔφ2φf ……(1)
ここで、
VA；ソース領域１２のポテンシヤルと注入領域
の表面のポテンシヤルとの間の電位間
lp；ソース領域１２から段差表面までの距離
Wp；ソール領域１２と基板１１との間の空乏層
幅
Δφ；注入領域の電位による空間電荷形成領域の
ポテンシヤルの低下
2φf；φfは基板１１のフエルミレベルである。Ｐ
型基板１１が反転するにはΔφとして2φfの値が
必要である。 VA/lp・WpΔφ2φf...(1) Here, VA ; potential lp between the potential of the source region 12 and the surface potential of the injection region; distance Wp from the source region 12 to the step surface; sole region 12 depletion layer width Δφ between the substrate 11 and the substrate 11 ; decrease in the potential of the space charge forming region 2φf due to the potential of the injection region; φf is the Fermi level of the substrate 11; P
In order to invert the mold substrate 11, a value of 2φf is required as Δφ.
(1)式より、lp＝1μm、NA＝1016atoms・cm-3、
VA＝7Vにすれば第２図に示す矢印Ｂの如く
Punch Through注入が起る。 From formula (1), lp = 1 μm, N A = 10 16 atoms cm -3 ,
If V A = 7V, it will look like arrow B shown in Figure 2.
Punch Through injection occurs.
本発明の構造を用いれば、浮遊ゲート電極１４
への電子注入が第２チヤンネル領域の広い領域に
わたつて行なわれるため、非常に高注入効率の
Punch Through注入型メモリになる。 Using the structure of the present invention, the floating gate electrode 14
Since electron injection is performed over a wide area of the second channel region, extremely high injection efficiency can be achieved.
Punch Through injection type memory.
本発明の基板の段差を設け、段差領域に注入領
域を設けたPunch Through注入型メモリの場合、
空間電荷形成領域のポテンシヤルは注入領域のポ
テンシヤルだけでなく、空間電荷形成領域の半導
体表面外部の電位により影響されることが考えら
れる。 In the case of the Punch Through injection memory of the present invention in which a step is provided on the substrate and an injection region is provided in the step region,
It is considered that the potential of the space charge forming region is influenced not only by the potential of the injection region but also by the potential outside the semiconductor surface of the space charge forming region.
第２図に示した本発明に関連する第１の参考例
は、そのような不安定性を除くために、半導体表
面にＰ型の高濃度領域１９を設けてある。高濃度
領域１９が空間電荷形成領域の半導体基板表面上
に設けてあるため、Punch Through現象は基板
１１の内部で起こる。従つて、Punch Through
現象は半導体外部電位に影響されず起こすことが
できる。第３図は、Punch Through現象がソー
ス・ドレイン領域間に起こり、浮遊ゲート電極１
４へ電子が注入される様子をバンド図で表わした
ものである。空間電荷形成領域のポテンシヤルが
Δφ2φf下がるとPunch Throughが起こる。 In the first reference example related to the present invention shown in FIG. 2, a P-type high concentration region 19 is provided on the semiconductor surface in order to eliminate such instability. Since the high concentration region 19 is provided on the surface of the semiconductor substrate in the space charge formation region, the Punch Through phenomenon occurs inside the substrate 11. Therefore, Punch Through
This phenomenon can occur without being affected by the external potential of the semiconductor. Figure 3 shows that the Punch Through phenomenon occurs between the source and drain regions, and the floating gate electrode 1
This is a band diagram showing how electrons are injected into 4. Punch Through occurs when the potential of the space charge formation region decreases by Δφ2φf.
次に、第４図に本発明に関連する第２の参考例
の断面図を示す。 Next, FIG. 4 shows a sectional view of a second reference example related to the present invention.
第２の参考例は、第１の参考例をさらに改良し
たもので、空間電荷形成領域のポテンシヤルを制
御する選択ゲート電極２５を設けたメモリであ
る。メモリの情報を読み出す場合には、本発明に
関連する第１の参考例の方法の他に、選択ゲート
電極２５の下のチヤネル領域を反転することによ
り、ソース・ドレイン領域間のコンダクタンスを
検出することによつても行うことができる。ま
た、書込み状態においては、空間電荷形成領域の
半導体基板表面が反転しないように選択ゲート電
極２５に電圧を印加する。Punch Thruogh現象
は、大部分半導体基板内部で起こる。 The second reference example is a further improvement of the first reference example, and is a memory provided with a selection gate electrode 25 that controls the potential of the space charge forming region. When reading information from a memory, in addition to the method of the first reference example related to the present invention, the conductance between the source and drain regions is detected by inverting the channel region under the selection gate electrode 25. It can also be done by Further, in the write state, a voltage is applied to the selection gate electrode 25 so that the surface of the semiconductor substrate in the space charge formation region is not inverted. Punch Thruogh phenomenon mostly occurs inside the semiconductor substrate.
次に、第５図に、本発明の実施例の断面図を示
す。第１及び第２参考例のメモリは、浮遊ゲート
電極の電位がドレイン領域の電位によつて制御さ
れるものであつた。第５図に実施例のメモリは、
浮遊ゲート電極３４の電位を制御するために、浮
遊ゲート電極３４の上に絶縁膜３８を介して制御
電極３９を新たに設けた構造である。ドレイン領
域３３と浮遊ゲート電極３４とは弱い容量結合す
るように形成されている。 Next, FIG. 5 shows a sectional view of an embodiment of the present invention. In the memories of the first and second reference examples, the potential of the floating gate electrode was controlled by the potential of the drain region. The memory of the embodiment shown in FIG.
In order to control the potential of the floating gate electrode 34, a control electrode 39 is newly provided on the floating gate electrode 34 with an insulating film 38 interposed therebetween. Drain region 33 and floating gate electrode 34 are formed to have weak capacitive coupling.
本発明の実施例のメモリにおいては、注入領域
のポテンシヤルはドレイン領域３３の電位と制御
ゲート電極３９の電位によつて変化する。メモリ
の読み出しは、選択ゲート電極３５と制御ゲート
電極３９に一定電圧を印加したときのソース・ド
レイン領域間のコンダクタンスを検出することに
より行なわれる。浮遊ゲート電極３４に電子が入
るとコンダクタンスは低下する。次に、メモリの
書込みは、選択ゲート電極３５に、空間電荷形成
領域の半導体表面が反転しないような電圧を印加
し、ドレイン領域３３及び制御ゲート電極３９に
大きなプログラム電圧を印加し、ソース領域３２
と注入領域との間に空間電荷領域を形成すること
によりPunch Through注入を行う。ソース領域
３２から空間電荷領域のポテンシヤルの山を越え
て段差領域の注入領域に入り、注入領域の空乏層
内で加速され浮遊ゲートに入る。 In the memory according to the embodiment of the present invention, the potential of the implanted region changes depending on the potential of the drain region 33 and the potential of the control gate electrode 39. Reading from the memory is performed by detecting the conductance between the source and drain regions when a constant voltage is applied to the selection gate electrode 35 and the control gate electrode 39. When electrons enter the floating gate electrode 34, the conductance decreases. Next, for memory writing, a voltage that does not invert the semiconductor surface in the space charge forming region is applied to the selection gate electrode 35, a large programming voltage is applied to the drain region 33 and the control gate electrode 39, and a large programming voltage is applied to the source region 32.
Punch through implantation is performed by forming a space charge region between the injection region and the injection region. From the source region 32, the light passes over the peak of the potential in the space charge region, enters the injection region of the step region, is accelerated within the depletion layer of the injection region, and enters the floating gate.
以上本発明のPunch Thruogh注入型半導体不
揮発性メモリは、半導体表面の段差領域に注入領
域を形成することにより、浮遊ゲート電極への電
子注入を面状に注入することを可能にした。従つ
て、本発明の半導体不揮発性メモリは、従来の
Punch Through注入型メモリに比べ、注入効率
が高く、高集積低プログラム電圧半導体不揮発性
メモリとなる。 As described above, the Punch Thruogh injection type semiconductor nonvolatile memory of the present invention makes it possible to inject electrons into the floating gate electrode in a planar manner by forming an injection region in a step region on the semiconductor surface. Therefore, the semiconductor nonvolatile memory of the present invention is different from the conventional semiconductor nonvolatile memory.
Compared to Punch Through injection type memory, it has higher injection efficiency and becomes a highly integrated, low program voltage semiconductor non-volatile memory.
本発明の説明に、Ｎ型メモリトランジスタを用
いたが、Ｐ型メモリトランジスタにおいても適用
できる。また、半導体基板は、絶縁膜上に設けら
れた半導体層の場合も含んでいる。 Although an N-type memory transistor is used in the description of the present invention, the present invention can also be applied to a P-type memory transistor. Further, the semiconductor substrate also includes a semiconductor layer provided on an insulating film.
また、本発明のメモリセルの書込み・読み出し
の選択は、ソース領域、基板、制御ゲート電極、
ドレイン領域、選択ゲート電極の電位を制御する
ことによつて容易に可能になる。書込み時の場
合、非選択のメモリセルに対しては、空間電荷形
成領域に空間電荷領域が形成されないようにする
必要がある。 In addition, selection of writing/reading of the memory cell of the present invention includes the source region, substrate, control gate electrode,
This can be easily achieved by controlling the potentials of the drain region and selection gate electrode. In the case of writing, it is necessary to prevent a space charge region from being formed in the space charge formation region for unselected memory cells.
第１図は、従来のPunch Through注入型半導
体不揮発性メモリの実施例の断面図、第２図、第
４図は本発明に関連するPunch Through注入型
メモリの第１、第２の参考例の断面図、第５図は
本発明のPunch Through注入型メモリの実施例
の断面図である。第３図は、第２図の矢印Ｂに沿
つたバンド構造図である。
１，１１，２１，３１……Ｐ型半導体基板、
２，１２，２２，３２……N+ソース領域、３，
１３，２３，３３……N+ドレイン領域、４，１
４，２４，３４……浮遊ゲート電極、５，２５，
３５……選択ゲート電極、６，７，８，１６，１
８，２６，２７，２８，３６，３７，３８……絶
縁膜。
FIG. 1 is a sectional view of an embodiment of a conventional Punch Through injection type semiconductor nonvolatile memory, and FIGS. 2 and 4 are first and second reference examples of Punch Through injection type memories related to the present invention. Cross-sectional view FIG. 5 is a cross-sectional view of an embodiment of the Punch Through injection type memory of the present invention. FIG. 3 is a band structure diagram along arrow B in FIG. 1, 11, 21, 31...P-type semiconductor substrate,
2, 12, 22, 32...N + source region, 3,
13, 23, 33...N + drain region, 4, 1
4, 24, 34... floating gate electrode, 5, 25,
35...Selection gate electrode, 6, 7, 8, 16, 1
8, 26, 27, 28, 36, 37, 38...Insulating film.
Claims (1)
基板と、前記半導体基板表面に前記段差領域を介
して高い表面側に設けられた第１導電型と逆導電
型である第２の導電型のキヤリア供給領域及び低
い表面側に設けられた第２導電型のキヤリア吸収
領域と、前記キヤリア供給領域の側方の前記段差
領域側面部表面に設けられた注入領域と、前記側
面部表面上に前記注入領域に対峙させて第１の絶
縁膜を介して設けられた浮遊ゲート電極と、前記
浮遊ゲート電極の電位を制御するために前記浮遊
ゲート電極上に第２の絶縁膜を介して設けられた
第１の制御ゲート電極とからなり、前記キヤリア
供給領域と前記注入領域との間の前記半導体基板
内に、前記注入領域と前記キヤリア供給領域との
間の電位差で空間電荷領域が形成されることを特
徴とするパンチスルー注入型半導体不揮発性メモ
リ。 ２ 前記空間電荷形成領域の表面に前記半導体基
板の不純物濃度よりも高い不純物濃度の第１導電
型の拡散層を設けたことを特徴とする特許請求の
範囲第１項記載のパンチスルー注入型半導体不揮
発性メモリ。 ３ 前記空間電荷領域上に第３の絶縁膜を介して
前記空間電荷領域形成領域の電位を制御する選択
ゲート電極を設けたことを特徴とする特許請求の
範囲第１項あるいは第２項記載のパンチスルー注
入型半導体不揮発性メモリ。[Scope of Claims] 1. A semiconductor substrate of a first conductivity type having a step region on its surface; and a semiconductor substrate of a conductivity type opposite to the first conductivity type provided on a higher surface side of the semiconductor substrate through the step region. a carrier supply region of a second conductivity type, a carrier absorption region of a second conductivity type provided on the lower surface side, and an injection region provided on the side surface of the stepped region on the side of the carrier supply region; a floating gate electrode provided on the surface of the side surface through a first insulating film so as to face the implanted region; and a second insulating film provided on the floating gate electrode to control the potential of the floating gate electrode. a first control gate electrode provided through a film, and a space is formed in the semiconductor substrate between the carrier supply region and the injection region by a potential difference between the injection region and the carrier supply region. A punch-through injection type semiconductor nonvolatile memory characterized in that a charge region is formed. 2. The punch-through injection type semiconductor according to claim 1, wherein a first conductivity type diffusion layer having an impurity concentration higher than that of the semiconductor substrate is provided on the surface of the space charge forming region. Non-volatile memory. 3. The method according to claim 1 or 2, characterized in that a selection gate electrode for controlling the potential of the space charge region formation region is provided on the space charge region via a third insulating film. Punch-through injection semiconductor non-volatile memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58147106A JPS6038881A (en) | 1983-08-11 | 1983-08-11 | Semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58147106A JPS6038881A (en) | 1983-08-11 | 1983-08-11 | Semiconductor nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6038881A JPS6038881A (en) | 1985-02-28 |
| JPH0481347B2 true JPH0481347B2 (en) | 1992-12-22 |
Family
ID=15422647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58147106A Granted JPS6038881A (en) | 1983-08-11 | 1983-08-11 | Semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6038881A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6419801A (en) * | 1987-07-15 | 1989-01-23 | Dx Antenna | Polarized wave discriminator |
| US5047812A (en) * | 1989-02-27 | 1991-09-10 | Motorola, Inc. | Insulated gate field effect device |
| US5467305A (en) * | 1992-03-12 | 1995-11-14 | International Business Machines Corporation | Three-dimensional direct-write EEPROM arrays and fabrication methods |
| US5594685A (en) * | 1994-12-16 | 1997-01-14 | National Semiconductor Corporation | Method for programming a single EPROM or flash memory cell to store multiple bits of data that utilizes a punchthrough current |
| US5808937A (en) * | 1994-12-16 | 1998-09-15 | National Semiconductor Corporation | Self-convergent method for programming FLASH and EEPROM memory cells that moves the threshold voltage from an erased threshold voltage range to one of a plurality of programmed threshold voltage ranges |
| US5557567A (en) * | 1995-04-06 | 1996-09-17 | National Semiconductor Corp. | Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data |
| US6051465A (en) * | 1997-07-30 | 2000-04-18 | Matsushita Electronics Corporation | Method for fabricating nonvolatile semiconductor memory device |
| US6121655A (en) * | 1997-12-30 | 2000-09-19 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
| US6051860A (en) * | 1998-01-16 | 2000-04-18 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
| US6147379A (en) * | 1998-04-13 | 2000-11-14 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2007158196A (en) * | 2005-12-07 | 2007-06-21 | Sharp Corp | Nonvolatile semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5353983A (en) * | 1976-10-27 | 1978-05-16 | Hitachi Ltd | Semiconductor non-volatile memory device |
-
1983
- 1983-08-11 JP JP58147106A patent/JPS6038881A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6038881A (en) | 1985-02-28 |
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