JPH048147U - - Google Patents

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Publication number
JPH048147U
JPH048147U JP1990047643U JP4764390U JPH048147U JP H048147 U JPH048147 U JP H048147U JP 1990047643 U JP1990047643 U JP 1990047643U JP 4764390 U JP4764390 U JP 4764390U JP H048147 U JPH048147 U JP H048147U
Authority
JP
Japan
Prior art keywords
card
signal
diagnosis
abnormality
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990047643U
Other languages
Japanese (ja)
Other versions
JP2500217Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990047643U priority Critical patent/JP2500217Y2/en
Priority to DE199090115578T priority patent/DE416331T1/en
Priority to DE0645685T priority patent/DE645685T1/en
Priority to DE69019441T priority patent/DE69019441T2/en
Priority to EP94117872A priority patent/EP0645685A3/en
Priority to EP90115578A priority patent/EP0416331B1/en
Priority to US07/572,899 priority patent/US5175864A/en
Priority to CN90107338A priority patent/CN1049924A/en
Priority to KR1019900013835A priority patent/KR930009638B1/en
Publication of JPH048147U publication Critical patent/JPH048147U/ja
Priority to US08/007,010 priority patent/US5339436A/en
Application granted granted Critical
Publication of JP2500217Y2 publication Critical patent/JP2500217Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Hardware Redundancy (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案のＩ／Ｏカード異常検出システ
ムの構成概念図、第２図は本考案システムを実施
するためのハードウエア構成図、第３図は本発明
システムを実施するためのソフトウエア構成図で
ある。 １……ＣＰＵシステム、１０……Ｉ／Ｏカード
異常検出手段、１１……Ｉ／Ｏカード・ドライバ
、１１１……自己診断機能、１１２……Ｉ／Ｏカ
ード切離し機能、２……Ｉ／Ｏカード群、２１…
…Ｉ／Ｏカード制御回路、１２，２２……ＣＰＵ
、１３，２３……メモリ、１４……ＣＰＵ側ゲー
ト・アレイ、２４……Ｉ／Ｏ側ゲート・アレイ、
Ｓ１……フエイル信号検知ドライバ、Ｓ２……Ｉ
／Ｏカード異常確認タスク、Ｓ３……カード・ド
ライバ、Ｓ４……フアームウエア及びレジスタ、
Ｓ５……ユーザ・プログラム。 Figure 1 is a conceptual diagram of the configuration of the I/O card abnormality detection system of the present invention, Figure 2 is a hardware configuration diagram for implementing the system of the present invention, and Figure 3 is a diagram of the software for implementing the system of the present invention. FIG. 1... CPU system, 10... I/O card abnormality detection means, 11... I/O card driver, 111... Self-diagnosis function, 112... I/O card separation function, 2... I/O Card group, 21...
...I/O card control circuit, 12, 22...CPU
, 13, 23...Memory, 14...CPU side gate array, 24...I/O side gate array,
S1...Fail signal detection driver, S2...I
/O card abnormality confirmation task, S3... card driver, S4... firmware and register,
S5...User program.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数枚のＩ／Ｏカードと、これらのＩ／Ｏカー
ドの動作を制御するＩ／Ｏカード・ドライバを有
するＣＰＵシステムとから構成され、前記ＣＰＵ
システムにて前記Ｉ／Ｏカードの異常を検出する
Ｉ／Ｏカード異常検出システムにおいて、前記Ｉ
／Ｏカードに異常を検出した際にフエイル信号を
出力する制御回路を設け、前記ＣＰＵシステムに
前記フエイル信号を受けて診断要求信号を発生す
る異常検出手段を設け、前記Ｉ／Ｏカード・ドラ
イバに、前記診断要求信号を受けて前記Ｉ／Ｏカ
ードに自己診断動作を行わせてその診断信号を受
信する自己診断機能部と、前記診断信号が異常を
表わす場合に前記制御回路に切離し信号を与えて
前記ＣＰＵシステムから切離し当該Ｉ／Ｏカード
・ドライバをエラー状態とする切離し機能とを設
けたことを特徴とするＩ／Ｏカード異常検出シス
テム。 It is composed of a plurality of I/O cards and a CPU system having an I/O card driver that controls the operation of these I/O cards.
In the I/O card abnormality detection system, the system detects an abnormality in the I/O card.
A control circuit is provided for outputting a fail signal when an abnormality is detected in the I/O card, an abnormality detecting means for receiving the fail signal and generating a diagnosis request signal is provided in the CPU system, and the I/O card driver is provided with an abnormality detection means for generating a diagnosis request signal in response to the fail signal. , a self-diagnosis function section that receives the diagnosis request signal, causes the I/O card to perform a self-diagnosis operation, and receives the diagnosis signal; and when the diagnosis signal indicates an abnormality, provides a disconnection signal to the control circuit. An I/O card abnormality detection system comprising: a disconnection function that disconnects the I/O card driver from the CPU system and puts the I/O card driver in an error state.
JP1990047643U 1989-08-31 1990-05-09 I/O card abnormality detection system Expired - Lifetime JP2500217Y2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP1990047643U JP2500217Y2 (en) 1990-05-09 1990-05-09 I/O card abnormality detection system
DE0645685T DE645685T1 (en) 1989-08-31 1990-08-14 Method for controlling a line computer for executing and relocating a translated program from a data storage collection.
DE69019441T DE69019441T2 (en) 1989-08-31 1990-08-14 Line computer.
EP94117872A EP0645685A3 (en) 1989-08-31 1990-08-14 Control method for an online computer for implementing and readressing a translated program from the collection of programs stored in memory.
EP90115578A EP0416331B1 (en) 1989-08-31 1990-08-14 Line computer
DE199090115578T DE416331T1 (en) 1989-08-31 1990-08-14 LINE COMPUTER.
US07/572,899 US5175864A (en) 1989-08-31 1990-08-24 Central processing unit in a computer system for controlling a manufacturing line
CN90107338A CN1049924A (en) 1989-08-31 1990-08-30 line computer
KR1019900013835A KR930009638B1 (en) 1989-08-31 1990-08-31 Line computer
US08/007,010 US5339436A (en) 1989-08-31 1993-01-21 Method of implementing a relocated compiled library program with an interpreter to control a manufacturing line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990047643U JP2500217Y2 (en) 1990-05-09 1990-05-09 I/O card abnormality detection system

Publications (2)

Publication Number Publication Date
JPH048147U true JPH048147U (en) 1992-01-24
JP2500217Y2 JP2500217Y2 (en) 1996-06-05

Family

ID=31563754

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990047643U Expired - Lifetime JP2500217Y2 (en) 1989-08-31 1990-05-09 I/O card abnormality detection system

Country Status (1)

Country Link
JP (1) JP2500217Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06309246A (en) * 1993-04-23 1994-11-04 Nec Corp Information processing system
JP2007058787A (en) * 2005-08-26 2007-03-08 Canon Inc Bridge and its error notification method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61260342A (en) * 1985-05-14 1986-11-18 Nec Corp Bus extender
JPS61262939A (en) * 1985-05-17 1986-11-20 Nec Corp Switching control system for system supervisory equipment
JPS62236056A (en) * 1986-04-07 1987-10-16 Nec Corp Input/output controller for information processing system
JPS6342252A (en) * 1986-08-07 1988-02-23 Tokyo Electric Co Ltd Terminal equipment provided with self-diagnostic function

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61260342A (en) * 1985-05-14 1986-11-18 Nec Corp Bus extender
JPS61262939A (en) * 1985-05-17 1986-11-20 Nec Corp Switching control system for system supervisory equipment
JPS62236056A (en) * 1986-04-07 1987-10-16 Nec Corp Input/output controller for information processing system
JPS6342252A (en) * 1986-08-07 1988-02-23 Tokyo Electric Co Ltd Terminal equipment provided with self-diagnostic function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06309246A (en) * 1993-04-23 1994-11-04 Nec Corp Information processing system
JP2007058787A (en) * 2005-08-26 2007-03-08 Canon Inc Bridge and its error notification method

Also Published As

Publication number Publication date
JP2500217Y2 (en) 1996-06-05

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