JPH048153U - - Google Patents
Info
- Publication number
- JPH048153U JPH048153U JP4613090U JP4613090U JPH048153U JP H048153 U JPH048153 U JP H048153U JP 4613090 U JP4613090 U JP 4613090U JP 4613090 U JP4613090 U JP 4613090U JP H048153 U JPH048153 U JP H048153U
- Authority
- JP
- Japan
- Prior art keywords
- dmac
- microprocessor
- terminal
- address
- forward direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- MHABMANUFPZXEB-UHFFFAOYSA-N O-demethyl-aloesaponarin I Natural products O=C1C2=CC=CC(O)=C2C(=O)C2=C1C=C(O)C(C(O)=O)=C2C MHABMANUFPZXEB-UHFFFAOYSA-N 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Microcomputers (AREA)
- Bus Control (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図は動作の一例を示すタイムチヤート、
第３図は従来装置の一例を示す構成ブロツク図で
ある。
１……マイクロプロセツサ、２……ダイレクト
・メモリ・アクセスコントローラ（ＤＭＡＣ）、
３……メモリ、４１……第１の１ビツトバツフア
、４２……第２の１ビツトバツフア、５……デコ
ーダ、ＤＢ……データバス、ＡＢ……アドレスバ
ス。
Fig. 1 is a configuration block diagram showing one embodiment of the present invention, Fig. 2 is a time chart showing an example of operation,
FIG. 3 is a block diagram showing an example of a conventional device. 1...Microprocessor, 2...Direct memory access controller (DMAC),
3...Memory, 41...First 1-bit buffer, 42...Second 1-bit buffer, 5...Decoder, DB...Data bus, AB...Address bus.
Claims (1)
アクセスコントローラ（ＤＭＡＣ）と、Ｉ／Ｏデ
イバイスで構成されるマイクロプロセツサ装置に
おいて、 前記マイクロプロセツサとＤＭＡＣとは異なつ
たビツト構成であり、 前記ＤＭＡＣのＡｏ端子と前記マイクロプロセ
ツサからＤＭＡＣのレジスタアクセスで使用しな
いアドレスＡｎ（ｎ＞０）線の間であつて、マイ
クロプロセツサからＤＭＡＣ側に順方向となるよ
うに接続した１ビツトバツフアと、 前記ＤＭＡＣのＡｏ端子とマイクロプロセツサ
のＡｏ端子の間であつて、ＤＭＡＣからマイクロ
プロセツサ方向側に順方向となるよう接続した１
ビツトバツフアと、 前記アドレスＡｎより大きなアドレスをデコー
ドとして前記ＤＭＡＣのチツプセレクトを行うデ
コーダと を設けたことを特徴とするマイクロプロセツサ装
置。[Scope of utility model registration claims] Microprocessor and direct memory
In a microprocessor device consisting of an access controller (DMAC) and an I/O device, the microprocessor and DMAC have different bit configurations, and there is a connection between the Ao terminal of the DMAC and the register of the DMAC from the microprocessor. A 1-bit buffer connected in the forward direction from the microprocessor to the DMAC side between the address An (n>0) lines that are not used for access, and the Ao terminal of the DMAC and the Ao terminal of the microprocessor. 1 connected in the forward direction from the DMAC to the microprocessor.
A microprocessor device comprising: a bit buffer; and a decoder that decodes an address larger than the address An and selects a chip of the DMAC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4613090U JPH048153U (en) | 1990-04-27 | 1990-04-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4613090U JPH048153U (en) | 1990-04-27 | 1990-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH048153U true JPH048153U (en) | 1992-01-24 |
Family
ID=31560938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4613090U Pending JPH048153U (en) | 1990-04-27 | 1990-04-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH048153U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211503U (en) * | 1975-07-15 | 1977-01-26 | ||
| JPS5280401U (en) * | 1975-12-15 | 1977-06-15 |
-
1990
- 1990-04-27 JP JP4613090U patent/JPH048153U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211503U (en) * | 1975-07-15 | 1977-01-26 | ||
| JPS5280401U (en) * | 1975-12-15 | 1977-06-15 |
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