JPH0481793A - Scroll display device - Google Patents

Abstract

PURPOSE:To improve the display performance by supplying image data to adjacent display elements in order in a scroll direction and sending unit data which are more than the display elements to the respective display elements within a unit scroll time. CONSTITUTION:Image data A and B displayed on a display unit 12 where the display elements Li,j are arrayed in matrix consist of unit data 13 which are supplied to every display elements Li,j and a memory 141 is stored with the unit data 13 which are more than the display elements Li,j. An output control part 15 supplies the image data A and B stored in the memory 14 to adjacent display elements Li,j in sequence in the scroll direction. At this time, the unit data 13 more than the display elements Li,j are sent out to the respective display elements Li,j within the unit scroll time for one image plane. Display contents in an intermediate scroll state between display contents at unit scroll time interval are displayed. Consequently, smooth and continuous scrolling operation is realized and the display quality is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a scroll display device that scrolls and displays still images on display means having display elements arranged in rows and columns.

BACKGROUND OF THE INVENTION Conventionally, LEDs (light emitting diodes) and various light sources are arranged in matrix to form a matrix type display device, and within the display area of the matrix type display device, characters such as letters and figures are displayed vertically or A configuration is known in which various data are sequentially displayed by scrolling in the horizontal direction.

FIG. 8 is a block diagram of a typical scroll display device (hereinafter abbreviated as display device) 1. The display device 1 includes display elements L1.2, . . . , Lm, where n<L when generic
) are arranged in a matrix of m rows and n columns, and unit data 3 that defines the lighting/stopping state of each display element corresponding to the display 2 is displayed before and after scrolling on the display 2. A memory 4 that stores display data A and B corresponding to two types of display contents, and an output control unit 5 that controls reading out image data A and B stored in the memory 4 and scrolling them on the display 2. It consists of:

The memory 4 has a storage capacity twice the number of display elements of the display 2, and the image data A is unit data a1j (i=1 to m, j) corresponding to the first display state on the display 2. =
1-0), and the image data B is composed of unit data bi,j (i=1~m, j=1~
n). Memory 4 stores unit data a in columns.
1. j ~ am, j ; bl, j ~ bm, j (
j=1 to n) with addresses adl, ad2, adn, ad
(n-j-1), 5, .ad2n are set.

FIG. 9 is a block diagram showing an example of the configuration of the output control section 5. As shown in FIG. The output control section 5 includes an oscillator 6 that outputs a shift clock SCK of a predetermined frequency, and the shift clock SCK is input as a clock signal to a counter C1 having 3-bit count outputs Q3 to Q1. The count outputs Q3 to Q1 are input to a three-man powered NAND circuit 7, and its output is output as a synchronization signal SY.

Further, the output control section 5 has a data input terminal that is connected to a reference voltage VD.
The inverting output Q of the flip-flop circuit FF is input to the AND circuit 8 together with the synchronizing signal SY, and the output of the AND circuit 8 is clocked to a counter C2 having 4-bit count outputs Q4 to Q1. Input as a signal.

The output Q3 of the second bit from the top of the counter C2 is applied to the clock input terminal C of the flip-flop circuit FF via the inversion circuit #r9. In addition, the low active reset input terminal R of the flip-flop circuit FF has
A start signal ST is supplied from outside.

The output of counter C2 is individually supplied to 4-bit input terminals P4-P1 of counter C3. The inverted synchronizing signal SY is input to the load signal terminal LD of the counter C3, and the shift clock SCK is input to the tarlock input terminal CK. Counter C3 has input terminal P
Up-count is performed from the numerical value input from 4 to P1, and the counting operation is cycled at 8 counts. counter C
The 4-bit outputs Q4-Q1 of 3 are input to the 4-bit address terminals A3-AO of the memory 4, and the 8-bit data D7-DO of the specified addresses adl-ad2n are inputted to the 4-bit address terminals A3-AO of the memory 4.
are output in parallel.

Data D7 to DO output at a certain timing are
Display elements LL, n, . . . of the display device 2 shown in the figure.

Lm is supplied in parallel to n to control these on/off operations. At the next timing, new data D7~
When Do is output, the data D7 to Do from the previous output are transferred to the adjacent display elements L1. n-1, . . . Lm, n-1, and new data D7 to DO control display elements LL, n, . . . Lm, n. In this way, each time the data D7 to DO are output from the memory 4, the image displayed on the display 2 scrolls from the right to the left in FIG.

FIG. 10 is a time chart explaining the operation of the conventional example, and FIG. 11 is a diagram explaining the scrolling operation of the conventional example. Start signal ST to flip-flop circuit FF
As shown in FIG. 10 (4), the inverting output terminal Q of the flip-flop circuit FF is at a low level, the counter C2 does not perform a counting operation, and the counter c3 performs a counting operation based on the shift clock SCK. The counting operation of count values from 0 to 7 is repeated.

That is, the display 2 continues to display, for example, the display shown in FIG. 11 (1) based on the display data DT1 of the image data A in the memory 4 shown in FIG. When the start signal ST is input to the flip-flop circuit FF at time t1 in FIG.
), the AND circuit 8 becomes conductive and supplies the synchronizing signal SY to the counter C2 as a clock signal.

The synchronization signal SY is a shift clock S from the NAND circuit 7.
It is generated every eight clocks of CK, that is, every unit scroll time Ts in FIG.

Therefore, the counter c3 is 8 of the shift clock scK.
A counting operation of 8 counts is started from the initial value which is increased by +1 every other clock. This state is the first
This is shown in Figure 0 (6). That is, the addresses adl, ad2, adn, ad (n+1), -1a of the memory 4
While eight consecutive addresses are being read out of d2n, the address range to be read out gradually extends from the left to the right in FIG. Therefore, on the display 2, a state in which a diagonal line having steps gradually scrolls to the left is displayed by display data DT2 to DT4 that are sequentially applied as shown in FIGS. 11(2) to 11(4).

Problems to be Solved by the Invention In the conventional example described above, in the scroll display of diagonal lines on the display 2, for example, the diagonal line displayed for each synchronization signal SY with one cycle of 8 clocks of the shift clock SCK is displayed as one display element. This will cause you to scroll to the left.

Since such a scrolling operation is performed at every unit scrolling time Ts shown in FIG. There is a problem with storing it away.

An object of the present invention is to solve the above-mentioned technical problems, to provide a scroll display device that realizes a scrolling operation with smooth continuity and has significantly improved display performance.

Means for Solving the Problems The present invention includes display means in which display elements are arranged in a matrix, and display data consisting of unit data given to each display means, which is composed of unit data equal to or greater than the number of display elements. a storage means for storing; and a storage means for sequentially applying the image data stored in the storage means to mutually adjacent display elements in a predetermined scrolling direction, and displaying an image based on the image data every unit scroll time corresponding to one display element. 1. A scroll display device comprising: output control means for scrolling, and output control means for sending unit data equal to or greater than the number of display elements to each display element within the unit scroll time.

Function The scroll display device according to the present invention uses display means in which display elements are arranged in rows and columns. The image data displayed on the display means is composed of unit data given to each display element, and the storage means stores more unit data than the number of display elements. The output control means sequentially applies the image data stored in the storage means to mutually adjacent display elements in a predetermined scroll direction, and displays an image based on the image data every unit scroll time corresponding to the display time of one screen. Scroll to . At this time, the output control means sends out more unit data than the number of display elements to each display element within the unit scroll time.

Therefore, the display means displays the display content in an intermediate scrolling state between the display content for each unit scroll time. Therefore, when performing a scrolling operation, a smooth and continuous scrolling operation is realized, and the quality of the scrolling operation of such a scroll display device is significantly improved.

Example In this example, a matrix type display device is constructed by arranging LEDs and various light sources in a matrix, and characters and figures are displayed vertically or horizontally within the display area of the matrix type display device. By scrolling in the direction of
The present invention relates to a scroll display device that sequentially displays various data. FIG. 1 is a block diagram of a scroll display device (hereinafter abbreviated as display device) 11 according to an embodiment of the present invention. The display device 11 includes display elements C1, L2, .
・, L'm, n (indicated when generic) is m rows
A display 12 arranged in a matrix of n columns, and a display 1
2, unit data 13 that defines the lighting/stopping state of each display element corresponds to 2 before and after scrolling on the display 12.
It includes a memory 14 that stores display data A and B corresponding to different types of display content, and an output control unit 15 that controls reading image data AB stored in the memory 14 and scrolling it on the display 12. configured.

The memory 14 has a storage capacity four times as large as the number of display elements of the display 12, and the image data A is stored in the first
m×2n unit data ai, j corresponding to the display state of
(i=1~m, j=1.151.2.2,5,..., n
, n, 5), and the image data B is composed of mx2n unit data bi,j (i=1
~m, j=1.15.2.2.5,..., n, n, 5)
It consists of

FIG. 2 is a block diagram showing an example of the configuration of the output control section 15. As shown in FIG. In the following explanation, an example where m=8 and n-8 will be explained. The output control unit 15 is
It is provided with an oscillator 16 which outputs a shift clock SCK of twice the predetermined frequency, and the shift clock SCK is input as a clock signal to a counter C1l having 4-bit count outputs Q4 to Q1.

The outputs Q4 to Q2 of the upper three bits of the counter C1l are A
The output of the AND circuit 17 is input to the NAND circuit 18 along with the output of the least significant bit Q1 of the counter C1l. The output of the least significant bit Q1 is
The output of the AND circuit 17 is inverted by the inverting circuit 19 and outputted as a shift clock SCK, and the output of the AND circuit 17 is inputted to the clock input terminal C of the flip-flop circuit FF1l, which is inputted to the data input terminal, and is inverted by the flip-flop circuit FFII. A synchronizing signal SY is output from the output terminal Q.

Further, the output control section 15 has a data input terminal that is connected to a reference voltage V.
It includes a flip-flop circuit FF12 connected to DD, and its inverted output Q is, together with the output of the NAND circuit 18,
The signal is input to an AND circuit 21, and its output is input as a clock signal to a counter C12 having 5-bit count outputs Q5 to Q1. Second from the top of counter C12
The bit-th output Q4 is applied to the clock input terminal of the flip-flop circuit FF12 via the inversion circuit 20. Further, a start signal ST is externally supplied to the low active reset input terminal R of the flip-flop circuit FF12.

The output of counter C12 is individually supplied to 5-bit input terminals P5-P1 of counter C13.

The load signal terminal LD of the counter C13 has the NAN
The output of the D circuit 18 is input, and the output from the oscillator 16 is input to the clock input terminal CK. The counter C13 performs up-counting from the numerical values input from the input terminals P5 to P1, and cycles the counting operation at 16 counts. 5-bit output Q5-Q of counter C13
1 is the 5-bit address terminal A4 to AO of the memo υ14.
8-bit data D7-DO of designated addresses adl-ad2n5 are output in parallel.

The 8-bit data output D7-DO from the memory 14 is
The signal is input to the flip-flop circuit FF13, and outputs data D7 to DO using the output from the least significant bit Q1 of the counter C1l as a tarok signal. That is, the counting operation of the counter C13 is performed based on a signal from the oscillator 16, and the flip-flop circuit F F 13 outputs input data with a clock signal having a cycle twice that of the clock signal from the oscillator 16. That is, the flip-flop circuit FF13 outputs only data at every other address regarding data from the memory 14 scanned by the address output from the counter C13.

Data D7 to D output at a certain timing.

are the display elements L1. of the display device 12 in FIG. n,...L
m and n in parallel to control their on/off operations.When new data D7-DO is output at the next timing, the data D7-Do from the previous output will be applied to the adjacent display element L1. .n-1,...Lm, controls the display operation of n-1, and new data D7 to DO are displayed on the display elements LL,
n, . . . , Lm, n is controlled. In this way, each time the data D7 to DO are output from the memory 14, the image displayed on the display 12 scrolls from the right to the left in FIG.

FIG. 3 is a block diagram showing the electrical configuration of the display 12. The display device 12 includes display elements L1,1 to L1 shown in FIG.
The number of latch circuits LC1 corresponds to the number n of columns of Lm,n.
The six-latch circuit LCI including ~LCn receives data D7~DO from the flip-flop circuit FF13 shown in the second diagram.
are input in parallel, output from output terminals Q7 to QO in parallel, and input in parallel to latch circuit LC2. Hereinafter, 8-bit output data from latch circuit LCk (k=1 to n-1) is input to latch circuit LC (k+1) in the same manner, and data transfer between each latch circuit LC is This is performed using a shift clock SCK that is commonly input to each of the latch circuits LCI to LCn.

On the other hand, each of the 8-hit outputs from the latch circuits LCI to LC'n is sent to the latch circuit LC which performs 8-bit input/output.
11, LC12,=-1 are input to LC1n, respectively. Display signal Yl,1 output from latch circuit LCII
6, Y2, 16, = -1Ym16 are given to the display elements Ll, 16 to Lm16 of the display 12, respectively, and the output Yl, 15, -1Ym, 15 of the latch circuit LC12 is given to the display elements L1.15 to Lm, Similarly, the outputs Y11, - from the latch circuit LC1n are given to
1Ym, 1 is given to display elements L1.1 to Lm, 1, respectively.

That is, the display data D7 to Do outputted from the flip-flop circuit FF13 shown in the second diagram is transmitted to the display elements Ll, 1
After displaying 6~Lm, 16, display elements LL, 15~L
m, 15 is displayed, and in the same manner, Ll, 1 to Lm, 1 are displayed.
Display.

FIG. 4 is a block diagram of the configuration related to display elements Li,j. One end of each display element Li,j is connected to a power source VO, and the other end is connected to a ground potential via a switching means 22 such as a transistor.

The switching means 22 receives the output Y via a resistor 23.
i and j are supplied to control on and off operations.

FIG. 5 is a time chart explaining the operation of this embodiment, FIG. 6 is a diagram explaining the state of image data in this embodiment, and FIG. 7 is a diagram explaining the display operation of this embodiment. It is. The start signal ST is a flip-flop circuit FF12.
5, the inverted output Q of the flip-flop circuit FF12 is at a low level as shown in FIG. 5(4), the counter C12 does not operate, and the counter C13
repeatedly counts numbers from 0 to 15. From the flip-flop circuit FF1B, for example, as shown in FIG. 6(1), every other address a of the memory 14 is
dl, ad2, .

When the start signal ST is input to the flip-flop circuit FF12 at time tll in FIG. 5, the inverted output Q becomes high level as shown in FIG.
conducts the clock signal from the NAND circuit 18. As shown in FIG. 5(2) and FIG. 5(5), the counter C12 performs the counting operation once, with 16 counts of the counter C1l being one cycle. The counter C13 performs a counting operation using the count value from the counter C12 as a count start value and a clock signal from the oscillator 16, with 16 counting operations as one cycle, as shown in FIG. 5(6). The count value from this counter C13 is calculated from the addresses adl, adl, and adl of the memory 14 shown in FIG.
5, ad2, ad25, -, adn, a
dn, 5, adn+1, ad2n, ad
It is input to the memory 14 as address data specifying 2n and 5.

On the other hand, the flip-flop circuit FF13 latches and outputs the data from the memory 14 every other period. This state is shown in FIG. 5(6) and FIG. 5(7).

Image data D7~ from flip-flop circuit FF13
DO is sequentially shifted to the latch circuits LC1 to LCn shown in FIG. 3 at a timing based on the shift clock SCK, and the image data from each latch circuit LC1 to LCn is input to the latch circuits LC1l to LC1n, respectively. , each display element L1. of the display device 12. j ~ Lm, j
(j = 1 to n) in parallel, respectively, and as shown in Fig. 5 (8
), the display 12 is displayed every cycle Tll based on the synchronization signal SY of
The display will take place.

When counter C1l performs 16 counting operations, NAN
The output of the D circuit 18 is inverted to low level, and the counter C1
Input the count clock to 2.

As a result, as shown in FIG. 5(2), the counter C12
The count value is incremented by +1 and becomes "1", and the counter C13 performs a counting operation 16 times from the count start value "1". At this time, the memory 14 uses the atsis data output from the counter C], 3.
As shown in Figure 6 (2), address ad1.5, a
The data of d2, ad2516, ad8.5, and ad9 are sequentially read out, and the flip-flop circuit FF13 reads every other address a as shown in FIG. 5(7).
d1.5, ad2.5. -1ad8.5 data is output in synchronization with shift clock SCK. The image shown in FIG. 7(2) is then displayed on the display 12.

Thereafter, the same operation as described above is repeated, and when the counter C1l performs the counting operation 16 times again, the output of the NAND circuit 18 is inverted to low level again, and the counter C12 increments the count value by +1.) ~ and set it as "2". Once, from memory 14, the image shown in Figure 6 (
3), attis ad2, ad2.5,
Data corresponding to ad3°ad9 and ad9.5 is read. From the flip-flop circuit FF13, as shown in FIG.
7), the addresses a, d2, ad3.
・The data corresponding to -1ad9 is output and the display 12
Then, an image as shown in FIG. 7 (3) will be displayed.

In this way, in this embodiment, the display 12 is stored in the memory 14.
The tenth
An intermediate scrolling state is displayed once during the unit scrolling time Ts of the conventional example shown in the figure, thereby making it possible to realize a smooth scrolling operation.

In the embodiment described above, although it is desired to interpose one interpolated display during the unit scroll period Ds, this interpolated display may be interposed a plurality of times. At this time, when the storage display is inserted twice, the data to be stored in the memory 14 will be multiplied by (k+1) for each image data AB.
A smoother scrolling operation can be performed. Furthermore, in the embodiment described above, the interpolated display is performed at an intermediate timing of the unit scroll period Ts, but it goes without saying that the timing of this interpolated display may be set at any timing.

Although the scrolling direction of the display 12 has been described in the above embodiment from right to left, it may be from left to right, or may be displayed in a vertically offset direction. Furthermore, a tilted scroll display may be performed by combining horizontal and vertical scrolling operations, and it goes without saying that the scrolling direction is not limited to a straight line but may be curved.

In the present embodiment, the display elements Li and j display two gradations of on/off, but the display data for each display element LiJ may be made into a plurality of bits to perform gradation display. Further, color display can be performed by setting the plurality of adjacent display elements Lj, j tones of red, green, and blue, for example. Further, in the above embodiment, although image data A related to the display screen before scrolling and image data B corresponding to the display screen after scrolling are set in the memory 14, the appearance or disappearance of only one screen can be scrolled. When performing this, only the image data for one screen is stored in the memory 14, and non-displayed data is stored when the count value of the counter C13 in FIG. 2 exceeds the address range of the data for one screen set in the memory 14. Effects of the Invention As described above, according to the present invention, the output control means may be configured to output specific data prepared separately in advance. The above unit data is sent to each display element. Therefore, the display means displays the display content in an intermediate scrolling state between the display content for each unit scroll time. Therefore, when performing a scrolling operation, a smooth and continuous scrolling operation is realized, and the quality of the scrolling operation of such a scroll display device is significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display device 11 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of an output control section 15.
3 is a block diagram showing a configuration example of the display device 12, FIG. 4 is a circuit diagram showing an electrical configuration related to display elements Li, j, and FIG. 5 is a time chart explaining the operation of this embodiment.
FIG. 6 is a diagram explaining the address range of the memory 14 in this embodiment, FIG. 7 is a diagram showing a display example of the display 12, FIG. 8 is a block diagram of the conventional display device 1, and FIG. FIG. 10 is a block diagram showing a configuration example of the output control section 5, FIG. 10 is a time chart explaining the operation of the conventional example, and FIG. 11 is a diagram explaining an example of the display of the display 2 in the conventional example. DESCRIPTION OF SYMBOLS 11...Display device, 12...Display device, 13...Unit data, 14...Memory, 15...Output control section, 16.Emitter, A, B.Image data, C1-C3...Counter , Li, j...Display element agent Patent attorney Keiichi Nishikyo

Claims (1)

[Scope of Claims] A display means in which display elements are arranged in a matrix, and a storage means for storing display data composed of unit data given to each display means in a number equal to or greater than the number of display elements. , output control means for sequentially applying the image data stored in the storage means to mutually adjacent display elements in a predetermined scrolling direction, and scrolling an image based on the image data every unit scroll time corresponding to one display element; A scroll display device comprising: output control means for sending unit data equal to or greater than the number of display elements to each display element within the unit scroll time.