JPH0481929A - Information processor - Google Patents

Abstract

PURPOSE:To improve the execution efficiency of an instruction by storing in advance an operand address of an instruction executed in the past in an operand address matrix, so that an operand address calculation stage, a cache access stage, an address conversion stage and an arithmetic stage can be executed simultaneously. CONSTITUTION:The processor has an instruction fetch stage, an operand address calculation stage, an address conversion stage and a cache access stage, and adopts a virtual storage system. In such a state, at every execution of an instruction, in an instruction address matrix 30 and an operand address matrix 31, its instruction address and operand address are registered, and subsequently, at the time of execution of its instruction, the addresses stored in these matrixes 30, 31 are used. Accordingly, an operand address calculation stage and a cache access stage, and also, an address conversion stage and an arithmetic stage can be executed simultaneously, respectively. In such a way, the execution efficiency of the instruction is improved.

Description

TECHNICAL FIELD The present invention relates to an information processing device, and more particularly to an information processing device that employs a virtual memory method and has each stage of instruction fetching, operand address calculation, address translation, cache access, and operation. It is something.

BACKGROUND OF THE INVENTION A command processing process in a conventional information processing device will be described with reference to the drawings. As shown in FIG. 2, in the instruction fetching stage, the instruction fetching circuit 11 uses the instruction address register 10
An instruction word 102 is taken out by the output 101 of and stored in the instruction register 14. At the same time, an instruction word length 103 is generated from the instruction word 102 by the instruction word length generation circuit 12,
The instruction address update circuit 13 generates an update address 104 from the instruction word length 103 and the output 101 of the instruction address register 10, and stores it in the instruction address register 10.

In the operand address calculation stage, instruction register 1
output 10B of general-purpose register 15 designated as address calculation input by output 105 of instruction register 1
0 output 105 and the operand address calculation circuit 16
and the result 108 is given to logical address register 1
7 is stored. At the same time, the output 10 of the instruction register 14
5, the output 107 of the general-purpose register 15 specified as the first operand is assigned to the first address translation stage.
It is stored in the operand register 19.

In the address translation stage, the logical address register 17
The output 109 of is converted into a physical address 110 by the address conversion circuit 18 and stored in the physical address register 20. At the same time, the output 111 of the first operand register 19 of the address translation stage is stored in the first operand register 52 of the cache access stage.

In the cache access stage, the output 112 of the physical address register 20 is given to the cache circuit 21 and stored as second operand data 113 in the second operand register 23 . At the same time, the output 114 of the first operand register 52 of the cache access stage
is stored in the first operand register 54.

In the calculation stage, the calculation circuit 25 performs calculations on the output 11B of the first operand register 54 and the output 115 of the second operand register 23, and the result is 11B.
7 is stored in the general-purpose register 15.

This type of information processing device requires five stages to process one instruction: instruction fetch, operand address calculation, address conversion, cache access, and operation, and because the instructions are executed sequentially, the instruction execution efficiency is low. There is.

OBJECTS OF THE INVENTION An object of the present invention is to provide an information processing device that can improve instruction execution efficiency.

Structure of the Invention According to the present invention, there is provided an information processing apparatus that has an instruction fetch stage, an operand address calculation stage, an address conversion stage, and a cache access stage and adopts a virtual memory method, in which the instruction fetch stage an instruction address matrix storage means indexed by the instruction address, an operand address matrix storage means indexed by the instruction address, a comparison means for comparing the instruction address and the instruction address from the instruction address matrix storage means, and the operand address calculation At the stage, operand address calculation means calculates an operand address using the output and displacement information of a general-purpose register indicated by the instruction taken out by the instruction address, and the instruction address matrix storage means is stored in the instruction address matrix storage means based on the comparison result of the comparison means. If it is determined that the instruction address to be executed next is registered, the cache access is immediately performed based on the physical page address information from the operand address matrix storage means and the in-page address information being output from the operand address calculation means. There is obtained an information processing device characterized in that it includes means for starting the operation of the stage.

Embodiment Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an instruction address register 10 for storing an instruction address, an instruction fetch path 11 for fetching an instruction according to an address 101 of this register 10, Based on the instruction word 102 from this circuit 11, the instruction word length is 10.
3, an instruction address update circuit 13 that generates an update address 104 based on the instruction word length 103 from this circuit 12 and the address from the register 10 and sends it to the instruction address register 10, and an instruction address register. Instruction address matrix memory 30 for reading two compartments in parallel with ten lower outputs 202
, two comparison circuits 32 and 33 which compare the outputs 203 and 204 from this memory 30 with the upper output 201 of the register 10, and which compartment of the memory 30 is selected based on the comparison results 205 and 20B of these circuits 32 and 33. A hit determination circuit 34 that determines whether or not an instruction to be executed next is registered and outputs a compartment selection signal 207 to select the compartment in the operand address matrix memory 31 that corresponds to the registered compartment. , an operand address matrix memory 31 that outputs two compartments from the positions specified by the lower outputs of the instruction address register 10, and a second compartment that selects one of the outputs 208 and 209 from this memory 31 by a selection signal 207. 1 selection circuit 35 is provided.

One of the features of one embodiment of the present invention is that the operand address calculation stage and the cache access stage are executed in parallel.

These stages include the output 105 of the instruction register 14.
A general-purpose register 15 outputting an output 10B indicated by
, a second selection circuit 36 that selects either the output 215 of the first selection circuit 35 or the output 210 of the address conversion circuit 18 based on the output 213 of the physical address comparison circuit 38;
a physical page address register 20 storing the output 211 of this second selection circuit 36; a cache circuit 21 accessed by the physical page address 112 from this register 20 and the in-page address in the output 108 of the operand address calculation circuit 16; An instruction register 14 that stores the instruction word 102 from the instruction fetch circuit 11, and an operand address calculation circuit that generates an operand address from the output 10B given from the general-purpose register 10B and the output 105 of the register 14 based on the output from the instruction register 14. 16, this circuit 16 includes a logical address register 17 for storing an operand address 10g generated by the circuit 16.

Further, an operand address calculation stage instruction address register 63 that stores the upper output 201 of the instruction address register 10, and an address translation stage instruction address register 64 that stores the output 220 of this register 63.
A cache access stage instruction address register 65 is provided to store the output 221 of this register 64.

Another feature of an embodiment of the present invention is that operations are performed in parallel in the address translation stage and the calculation stage.

These stages include an address conversion stage physical address register 37 that stores the physical page address 112 from the register 12, an address conversion circuit 18 that converts the logical address 109 from the register 17 to a physical page address 110, and a physical address register 37 that stores the physical page address 112 from the register 12; Physical page address 2 from page address 110 and register 37
12, a D flip-flop (F/F) 39 that stores the comparison result 21B of this circuit 38, and a first operand 10 outputted from the general-purpose register 15 by the output 105 of the instruction register 14.
Address translation stage first operand register 19 storing 7, second operand 1 from cache circuit 21
a second operand register 23 that stores 13;
Contains 5.

Next, the operation of one embodiment of the present invention will be described in detail with reference to FIG.

Referring to FIG. 1, in the instruction fetching stage of the instruction processing process according to an embodiment of the present invention, the instruction fetching circuit 11 uses the output 101 of the instruction address register 10 to
2 and stores it in the instruction register 14. At the same time, from the instruction word 102, the instruction word length generation circuit 12 generates an instruction word length of 1
03 is generated, and the instruction word address update circuit 13 generates an update address 104 from the instruction word length 103 and the output 101 of the instruction address register 10, and stores it in the instruction address register 10. The upper output 201 of the instruction address register 10 is stored in the address register 63 of the operand address calculation stage.

Furthermore, the lower output 202 of the -instruction address register 10 is given to the instruction address matrix memory 30 and the operand address matrix memory 31. Comparison circuits 32 and 33
are the outputs 203, 2 of the two compartments of the instruction address matrix memory 30 indicated by the given address.
04 with the upper output 201 of the instruction address register 10, and the comparison results 205 and 206 are provided to the hit determination circuit 34.

This hit determination circuit 34 is connected to the instruction address matrix memory 3.
The compartment selection signal 207 is first set to determine in which compartment of 0 the instruction to be executed next is registered, and to select the compartment of the operand address matrix that corresponds to the registered compartment. is sent to the selection circuit 35. This first selection circuit 35 selects the two compartment outputs 208 and 209 of the operand address matrix memory 31 according to the compartment selection signal 207, and
is sent to the selection circuit 36. The second selection circuit 36 then selects the output 210 of the first selection circuit 35 and stores it in the physical page address register 20.

In the operand address calculation stage, instruction register 1
4, the output 106 of the general-purpose register 15 specified as the address calculation input and the output 105 of the instruction register 14 are output to the operand address calculation circuit 1.
6, and the result 108 is stored in the logical address register 17.

At the same time, the output 105 of the instruction register 14 causes the first
Output 1 of general-purpose register 15 specified as operand
07 is stored in the first operand register 19 of the address translation stage.

Further, the output 220 of the instruction address register 63 of the operand address calculation stage is stored in the instruction address register 64 of the address translation stage.

Furthermore, the output 112 of the physical address register 20 and the intra-page address information in the calculation result 108 of the operand address calculation circuit 16 are given to the cache circuit 21,
The second operand data 113 is stored in the second operand register 23 .

The output 112 of the physical address register 20 is also stored in the physical address register 37 of the address translation stage.

Further, the output 221 of the instruction register 64 of the address translation stage is stored in the instruction address register 65 of the cache access stage.

In the address translation stage, the logical address register 17
The output 109 of is converted into a physical address 110 by the address conversion circuit 18. The physical page address translation circuit 38 compares the physical address 110 with the output 212 of the physical address register 37 of the address translation stage,
A comparison result 213 is output. If the comparison result 213 indicates a match, the general-purpose register 15 stores the operation result 117 of the output 111 of the first operand register 19 and the output 115 of the second operand register 23 of the address translation stage.
is stored, and the processing of one instruction is completed.

If a mismatch is indicated, the update operations of the instruction address register 10, instruction register 14, general-purpose register 15, and logical address register 17 are all inhibited, and
The second selection circuit 36 selects the physical page address information in the physical address 110 as its output 211 and stores it in the physical address register 20. Also comparison result 21
3 is stored in a D type flip-flop 39.

Then, in the next cycle, the output 112 of the physical page address register 20 and the intra-page address information in the calculation result 108 of the operand address calculation circuit 16 are given to the cache circuit 21, and the second operand data l13
is stored in the second operand register 23, and simultaneously the output 112 of the physical page address register 20 is stored in the physical page address register 37 of the address translation stage. In addition, D type flip-flop 3
9 stores the physical page address in the output 112 of the physical page address register 20 in the operand address matrix 31. At the same time, the output 222 of the instruction address register 65 at the cache access stage is stored in the instruction address matrix 30.

Furthermore, in the next cycle, the address conversion stage is performed again, and this time, the output 2 of the physical page address comparison circuit 38 is
Since 13 indicates a match, the instruction processing ends.

By doing this, the instruction address and operand address will be registered in the instruction address matrix 30 and operand address matrix 31 each time the instruction is executed, so the next time the instruction is executed, these matrices 30.31
You can use the address stored in . In this case, the operand address calculation stage and the cache access stage, as well as the address translation stage and the calculation stage, can be executed simultaneously.

Note that the physical page address comparison circuit 38 compares the physical page address 112 of the physical page address register 20 and the physical page address 110 of the address conversion circuit 18 to find a match, because the content of the general-purpose register 15 is It is determined whether the physical page address 210 selected by the second selection circuit 36 has become invalid due to rewriting or the like.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention stores the physical page addresses of operands of instructions that have been executed in the past in an operand address matrix. Since the conversion stage and the arithmetic stage can be executed simultaneously, the efficiency of instruction execution is higher on average than in the past.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional information processing apparatus. Explanation of symbols of main parts 10...Instruction address register 11...
Instruction fetch circuit 12...Instruction word length generation circuit 13...Instruction address update circuit 14...
Instruction register 15...General-purpose register 16...Operand address calculation circuit 17...
...Logical address register 18...Address translation circuit 19...First operand register 20 of address translation stage...Physical page address register 21...
... Cache circuit 23 ... Second operand register 25 ...
- Arithmetic circuit 30, . . . instruction address matrix 31 . . . operand address matrix 32, ! 1
13...-Comparison circuit 34...Hit judgment circuit 35...First selection circuit 36...Second selection circuit 37... Address translation stage physical page address register

Claims (1)

[Claims] (1) An information processing device that employs a virtual memory system and has an instruction fetch stage, an operand address calculation stage, an address translation stage, and a cache access stage, wherein the instruction address is indexed by the instruction address in the instruction fetch stage. a matrix storage means, an operand address matrix storage means indexed by the instruction address, a comparison means for comparing the instruction address and the instruction address from the instruction address matrix storage means;
In the operand address calculation stage, operand address calculation means calculates an operand address using the output and displacement information of a general-purpose register indicated by the instruction taken out by the instruction address, and the instruction address is calculated based on the comparison result of the comparison means. If it is determined that the instruction address to be executed next is registered in the matrix storage means, the address of the next instruction to be executed is registered from the physical page address information from the operand address matrix storage means and the in-page address information being output from the operand address calculation means. and means for immediately starting the operation of the cache access stage.