JPH0481933A - Vector data processor - Google Patents

Abstract

PURPOSE:To prevent the decrease of a data transfer processing speed by referring to the contents of an information storage circuit, and saving only effective data to a main storage from data stored in a vector register. CONSTITUTION:When an area allocating instruction of a vector register is received through a control line 16 from a software, an instruction control circuit 11 sets a value designated by a software to an information storage circuit 2 through a data line 8. That is, the information storage circuit 2 becomes a pointer for showing an effective area in the vector register. When a saving instruction is received from the instruction control circuit 11, a drawback control circuit 12 resets a pointer register 14 through a control line 18, issues a write request to a specific address of a main storage device 100 through a control part 7, and executes a data drawback to only an area shown by the pointer. In such a way, a decrease of a data transfer processing speed can be suppressed to the minimum.

Description

TECHNICAL FIELD The present invention relates to a vector data processing apparatus, and more particularly to a vector data processing apparatus having a saving means for saving the contents of a vector register to a main memory when switching tasks.

Prior Art Conventionally, vector data processing devices of this type operate under a multiple programming scheme. Therefore, it is necessary to switch tasks by interrupting the execution of one program and executing another program. At this time, the intermediate results of the program whose execution is to be interrupted must be saved in main memory. Its operation will be explained with reference to FIG.

When the vector data processing device is executing a certain program, the vector register 1 contains data supplied to the arithmetic and logic operation circuit 3 through the data line 5 and processing results of the arithmetic and logic operation means 3 obtained through the data line 6. Stored.

In general, a vector register is a sequence of a very large number of registers (hereinafter referred to as element registers), so numbers are assigned in order from the first element register, and each element register is assigned an element number L (imp, 1, 2, . . . ...)'s element register"
Expressed as.

On the other hand, FIG. 3 is a detailed internal diagram of the control circuit 4. As shown in FIG.

When the command control circuit 11 receives a task switching command from software through the control line 16, it issues a save command to the save control circuit 12 through the control line 17, and stores the value specified by the software in the stack pointer 13 through the data line 8. . Note that details will be described later.

When the save control circuit 12 receives the save command, it resets the pointer register 14 through the control line 18 and issues a write request to a specific address in the main storage device 100 through the control line 7. Here, the specific address is a save area that forms part of the main memory, and data is always saved to this save area.

In addition, in the multiple programming method, a part of the save area is allocated to each program, and the software collects information about the save area, such as from what address to what address a certain program has secured the save area, and what address it currently has. The company monitors whether it is being used up to the point in time.

The value specified by the software that the instruction control circuit 11 stores in the stack pointer 13 via the data line 8 is an address pointing to the save area allocated to the program. Therefore, by referring to the contents of stack pointer 13 through data line 24, main memory 100 can obtain the specific address to which the pig should be written.

The pointer register 14 always stores a value j (j is an element number, which can be considered as element number 0 at first) that points to an arbitrary element register of the vector register 1, and the value j that points to an arbitrary element register of the vector register 1 is stored in the pointer register 14. Data in the element registers is output to main memory 100 via data line 10.

The main memory device 100 is connected to the save control circuit 12 through the control line 7.
When receiving a write request from , the data obtained through the data line 10 is written to the address in the main memory that the stack pointer 13 points to through the data line 24 .

On the other hand, the comparison circuit 15 inputs the content j of the pointer register 14 through the data line 21 and compares it with the maximum value of the element number of the vector register 1. Note that k is a constant.

When the comparison result is k>j, the comparison 1 circuit 15 determines that there is still data to be saved, and the save control circuit 12
does not give any instructions. However, the comparison results -
j, it is determined that there is no more data to be saved, and an instruction to finish saving is given to the save control circuit 12 via the control line 22.

If there is no instruction from the comparator circuit 15, the save control circuit 12
The contents of the pointer register 14 are incremented through the control line 18 and the stack pointer 1 is incremented through the control line 23.
After incrementing the contents of 3, a write request is issued to the main storage device 100 via the control line 7.

Thereafter, by repeating the same operation, all the data in the vector register 1 will be saved.

In other words, in the conventional vector data processing device described above,
When switching tasks, all data held in the vector registers is saved to main memory. Therefore, even if the necessary data is written to only a part of the vector register at the time of saving data, saving all the data in the vector register is wasteful and will lead to a decrease in the overall processing speed. There is a drawback.

OBJECT OF THE INVENTION The present invention has been made in order to solve the above-mentioned conventional drawbacks, and its purpose is to provide vector data that can minimize the reduction in processing speed when transferring data from the vector register to the main memory. The purpose of the present invention is to provide a processing device.

Composition of the Invention A vector data processing device according to the present invention includes a main memory, a vector register that holds vector data related to a task being executed, and a vector register that saves vector data in the vector register to the main memory when switching tasks. A vector data processing device comprising a data saving means for
A pointer indicating an area allocated to the task immediately before switching among the storage areas of the vector register, and a save control means for saving data only to the area indicated by the pointer among the storage areas of the vector register. It is characterized by

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a vector data processing apparatus according to the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

In the figure, when the vector data processing device is executing a certain program, the vector register 1 contains data that is supplied to the arithmetic and logic circuit 3 through the data line 5, and the processing results of the arithmetic and logic circuit 3 that are obtained through the data line 6. etc. are stored.

The value i stored in the information storage circuit 2 indicates that the area of the vector register 1 that can be used by this program is element number 0.
Indicates that it is an element register of ~i. Therefore, a program is not allowed to access an element register with a size exceeding element number i.

FIG. 4 is a block diagram showing the internal configuration of the control circuit 4, and parts equivalent to those in FIG. 3 are designated by the same symbols.

When the command control circuit 11 receives a vector register area allocation command from software through the control line 16, it sets a value i specified by the software in the information storage circuit 2 through the data line 8. In other words, the information storage circuit 2 serves as a pointer indicating a valid area in the vector register.

The command control circuit 11 is also connected to a control line 16 by software.
When a task switching command is received through the control line 17, a save command is issued to the save control circuit 12 via the control line 17, and a value specified by software different from i is stored in the stack pointer 13 via the data line 8. Note that details will be described later.

When the save control circuit 12 receives the save command from the command control circuit 11, it resets the pointer register 14 through the control line 18, and issues a write request to a specific address of the main storage device 100 through the control line 7.

Here, the specific address is a save area that forms part of the main memory, and data is always saved to this save area.

In addition, in the multiple programming method, a part of the save area is allocated to each program, and the software stores information about the save area, for example, which address of the save area is reserved for a certain program, and what address it is currently in the save area. It manages whether even the street address is being used.

The value specified by the software that the instruction control circuit 11 stores in the stack pointer 13 via the data line 8 is an address pointing to the save area allocated to the program. Therefore, by referring to the contents of stack pointer 13 through data line 24, main memory device lOO can obtain a specific address at which to write data.

The pointer register 14 contains a value j (j is the element number,
Initially, the element number O) is always stored,
Data in the element register pointed to by pointer register 14 through data line 9 is output to main memory 100 through data line 10 .

The main memory 100 is connected to the save control circuit 12 through the control line 7.
When a write request is received from , the data in the vector register 1 obtained through the data line 1° is written to the address in the main memory pointed to by the stack pointer 13 through the data line 24.

On the other hand, the comparison circuit 15 inputs the content i of the information storage circuit 2 and the content j of the pointer register through data lines 20 and 21, respectively, and compares the sizes of the two. When the comparison result is i>j, the comparison circuit 15 determines that there is still data to be saved and does not issue any instructions to the save control circuit 12.

However, if the comparison result is ij, it is determined that there is no more data to be saved, and an instruction to finish saving is given to the save control circuit 12 via the control line 22.

If there is no instruction from the comparison circuit 15, the save control circuit 12 increments the contents of the pointer register 14 through a control line 18, increments the contents of the stack pointer 13 through a control line 23, and then increments the contents of the stack pointer 13 through a control line 7. A write request is issued to the device 100.

Similarly, only valid data in the element registers with element numbers 0 to i are saved to the main storage device 100.

Note that the present invention can also be applied to data other than vector data (scalar data). However, since the total number of scalar data used by general programs is only a fraction of the vector data used by vector calculation programs, no effect can be obtained.

DETAILED DESCRIPTION OF THE INVENTION As described above, in the present invention, the control circuit refers to the contents of the information storage circuit and saves only valid data from among the data stored in the vector register to the main memory, thereby achieving data transfer. This has the effect of reducing the time required for processing and minimizing the reduction in processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a vector data processing device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional vector data processing device, and FIG. 3 is a block diagram showing the configuration of a conventional vector data processing device. A block diagram showing the internal configuration, Figure 4 is the first
FIG. 2 is a block diagram showing the internal configuration of a control circuit shown in the figure. Explanation of symbols of main parts 1... Vector register 2... Information storage circuit 3... Arithmetic logic operation circuit 4... Control circuit 100...・Main memory

Claims (1)

[Claims] (1) Main memory and vector registers that hold vector data related to the task being executed, and when switching tasks,
A vector data processing device comprising: data saving means for saving vector data in the vector register to the main memory; a pointer indicating an area allocated to a task immediately before switching among the storage areas of the vector register; A vector data processing device comprising a save control means for saving data only to the area indicated by the pointer among the storage areas of the vector register.