JPH0482252A - Mounting structure of semiconductor integrated circuit - Google Patents

Mounting structure of semiconductor integrated circuit

Info

Publication number
JPH0482252A
JPH0482252A JP2196471A JP19647190A JPH0482252A JP H0482252 A JPH0482252 A JP H0482252A JP 2196471 A JP2196471 A JP 2196471A JP 19647190 A JP19647190 A JP 19647190A JP H0482252 A JPH0482252 A JP H0482252A
Authority
JP
Japan
Prior art keywords
ground
package substrate
interconnection layer
circuit board
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2196471A
Other languages
Japanese (ja)
Other versions
JP2919010B2 (en
Inventor
Hitoshi Ishizuki
石附 仁
Kiyoto Higa
比嘉 清人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP2196471A priority Critical patent/JP2919010B2/en
Publication of JPH0482252A publication Critical patent/JPH0482252A/en
Application granted granted Critical
Publication of JP2919010B2 publication Critical patent/JP2919010B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs

Landscapes

  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a high-density mounting operation by a method wherein a ground interconnection layer protrudes over the whole outer-circumferential side face of a package substrate and this protruding part is connected electrically to a surface pad of a ground layer on a printed-circuit board. CONSTITUTION:A ground interconnection layer 1 is set in a buried state nearly over the whole face inside an insulating package substrate 3. The ground interconnection layer 1 is buried and attached so as to protrude nearly uniformly over the whole side face (four side faces in the case of a square substrate) of the package substrate 3. Said protruding part of the ground interconnection layer 1 is connected electrically, by using a grounding connection member 2, to a ground surface pad 8 of a ground interconnection layer 12 on a printed- circuit board 9.

Description

【発明の詳細な説明】 技術分野 本発明は半導体集積回路実装構造に関し、特に多ピン半
導体集積回路収納用のパッケージを含む実装構造に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor integrated circuit mounting structure, and more particularly to a mounting structure including a package for housing a multi-pin semiconductor integrated circuit.

従来技術 従来のこの種のパッケージの実装構造では、信号電位の
基準となるグランド(接地)端子は信号端子と同一形状
となっており、このグランド端子はプリント配線板に対
しては信号端子と同様に半田付は等により接続されてい
る。
Prior Art In the conventional mounting structure of this type of package, the ground terminal, which serves as the reference for the signal potential, has the same shape as the signal terminal. are connected by soldering etc.

第4図はこの様なパッケージ実装構造の一部縦断図面を
示す。半導体集積回路チップ(以下1cチツプと称す)
5は絶縁性のパッケージ基板3の−主面に搭載されてい
る。
FIG. 4 shows a partial longitudinal sectional view of such a package mounting structure. Semiconductor integrated circuit chip (hereinafter referred to as 1c chip)
5 is mounted on the main surface of the insulating package substrate 3.

このICチップ5の入出力ピン51は接続線6を介して
パッケージ内部導体配線パターン4に接続されている。
Input/output pins 51 of this IC chip 5 are connected to the package internal conductor wiring pattern 4 via connection lines 6.

この配線パターン4はパッケージ基板3に突出して取付
けられたり一ト線]0に接続されている。
This wiring pattern 4 is attached to the package substrate 3 in a protruding manner and is connected to the one-tone wire ]0.

このリード線10はプリント基板9上の表面パッド7に
半田付けにて接続されている。このプリント基板9には
多層構造の配線パターン11,12が設けられており、
このプリント基板9の表面に表面パッド7が印刷して配
置されている。
This lead wire 10 is connected to a surface pad 7 on a printed circuit board 9 by soldering. This printed circuit board 9 is provided with wiring patterns 11 and 12 having a multilayer structure.
A surface pad 7 is printed and arranged on the surface of this printed circuit board 9.

この様な従来のICパッケージの実装構造では、収納実
装されるICチップ5の信号端子数が多く多ピン構成に
なると、それに伴って信号電位の基準となるグランド端
子の動作ノイズを抑圧するために、グランド端子も信号
端子数に比例して多数必要となってくる。よって、IC
パッケージか大型化してプリント配線板上への高密度実
装の妨げになるという欠点かある。
In such a conventional IC package mounting structure, when the number of signal terminals of the IC chip 5 to be housed and mounted increases and the configuration becomes a multi-pin configuration, it is necessary to suppress the operation noise of the ground terminal, which is the reference of the signal potential. , a large number of ground terminals are required in proportion to the number of signal terminals. Therefore, I.C.
The disadvantage is that the package becomes larger, which impedes high-density mounting on printed wiring boards.

また、パッケージの大型化を抑止すべくクランド端子を
増加させずに、信号端子のみを増大すると、信号端子の
電気的動作によってグランド端子に動作ノイズか重畳し
てしまい、回路動作の信頼性か低下するという欠点があ
る。特に、回路を高速で動作させると、信頼性の低下は
顕著になるという欠点がある。
Furthermore, if only the number of signal terminals is increased without increasing the number of ground terminals in order to prevent the package from becoming larger, the electrical operation of the signal terminals will cause operational noise to be superimposed on the ground terminal, reducing the reliability of circuit operation. There is a drawback that it does. In particular, when the circuit is operated at high speed, there is a disadvantage that the reliability decreases significantly.

発明の目的 本発明の目的は、パッケージの大型化を招く二となくク
ランド端子を実質上増大するようにして、回路の信頼性
の向上を図った半導体集積回路実装構造を提供すること
である。
OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit mounting structure in which the number of ground terminals is substantially increased, which would otherwise lead to an increase in the size of the package, thereby improving the reliability of the circuit.

発明の構成 本発明によれば、半導体集積回路チップを搭載した絶縁
性のパッケージ基板と、このパッケージ基板に突出して
取付けられ前記チップの入出力ビンと接続されたリード
線と、前記リート線と接続された表面バッドを有するプ
リント基板とを含む半導体集積回路実装構造であって、
前記絶縁性のパッケージ基板に埋設されこのパッケージ
基板の側面から略一様に突出して設けられた導体からな
るグランド層と、前記グランド層の突出部と前記プリン
ト基板の表面バットのクランドバットとの間を電気的に
接続したグランド接続部材とを含むことを特徴とする半
導体集積回路パッケージが得られる。
Structure of the Invention According to the present invention, there is provided an insulating package substrate on which a semiconductor integrated circuit chip is mounted, a lead wire attached to the package substrate in a protruding manner and connected to an input/output bin of the chip, and a lead wire connected to the lead wire. A semiconductor integrated circuit mounting structure comprising: a printed circuit board having a surface pad;
a ground layer made of a conductor embedded in the insulating package substrate and protruding substantially uniformly from a side surface of the package substrate; and between the protrusion of the ground layer and the ground butt of the surface butt of the printed circuit board. and a ground connection member electrically connected to the ground connection member.

実施例 以下に図面を用いて本発明の詳細な説明する。Example The present invention will be described in detail below using the drawings.

第1図及び第2図は本発明の実施例の一部縦断面図であ
り、断面を異にした場合のものである。
FIGS. 1 and 2 are partial vertical cross-sectional views of an embodiment of the present invention, with different cross-sections.

両図において、第4図と同等部分は同一符号により示し
ている。
In both figures, parts equivalent to those in FIG. 4 are indicated by the same reference numerals.

第4図の従来例との差異部分につき述べると、絶縁性の
パッケージ基板3内には略全面に亘ってグランド配線層
1か埋設された状態にある。このグランド配線層1はパ
ッケージ基板3の側面(方形状基板であれば4つの側面
)全てに亘って略一様に突出して埋設され、取付けられ
ているものとする。
Regarding the difference from the conventional example shown in FIG. 4, the ground wiring layer 1 is buried almost entirely within the insulating package substrate 3. It is assumed that the ground wiring layer 1 is embedded and attached so as to protrude substantially uniformly from all sides of the package substrate 3 (four side surfaces in the case of a rectangular substrate).

このグランド配線層1の当該突出部分と、プリント基板
9のグランド配線層12のグランド表面バッド8とはグ
ランド接続部材2により電気的に接続されている。
The protruding portion of the ground wiring layer 1 and the ground surface pad 8 of the ground wiring layer 12 of the printed circuit board 9 are electrically connected by a ground connecting member 2 .

第3図はこのグランド接続部材2を第1,2図の実装構
造から切離した状態を示しており、このグランド接続部
材2がパッケージ基板3の全側面に突出したグランド配
線層1及びグランド表面バッド8に半田付けして固定さ
れる。
FIG. 3 shows a state in which this ground connection member 2 is separated from the mounting structure shown in FIGS. It is fixed by soldering to 8.

尚、他の構造は第4図の従来例と同一であり、その説明
は省略する。
Note that the other structures are the same as the conventional example shown in FIG. 4, and their explanation will be omitted.

発明の効果 この様に、パッケージ基板3の外周側面全面に亘りグラ
ンド配線層1を突出させ、この突出部とプリント基板9
のグランド層]2の表面パッド8とを半田付は等により
接続する構成としたので、信号端子が増加してもグラン
ド端子はそれに伴って増加する必要がなく、よって高密
度実装が可能となる。
Effects of the Invention In this way, the ground wiring layer 1 is made to protrude over the entire outer peripheral side surface of the package substrate 3, and this protrusion and the printed circuit board 9
The ground layer] 2 is connected to the surface pad 8 by soldering, etc., so even if the number of signal terminals increases, there is no need to increase the number of ground terminals accordingly, making high-density mounting possible. .

また、同時に、グランドとの接続面積が増大し、かつ信
号ピンは全てグランドと近接するようになるので、IC
チップの動作ノイズの影響を受けにく く な る。
At the same time, the connection area with the ground increases, and all signal pins come close to the ground, so the IC
Less susceptible to chip operation noise.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明の実施例の縦断面を夫々示す
図、第3図は第1.2図のクランド部材を切離して示し
た縦断面図、第4図は従来のICチップ実装構造を示す
縦断面図である。 主要部分の符号の説明 1、]2・・・・・・グランド配線層 2・・・・・・グランド接続部材 3・・・・・・パッケージ基板 5・・・・・・ICチップ 6・・・・・・接続線 7.8・・・・・・表面パッド 10・・・・・・リード線 51・・・・・ICピン 出願人 日本電気株式会社(外1名)
1 and 2 are longitudinal cross-sectional views of an embodiment of the present invention, FIG. 3 is a vertical cross-sectional view of the clamp member shown in FIGS. 1 and 2, cut away, and FIG. 4 is a conventional IC chip. FIG. 3 is a vertical cross-sectional view showing the mounting structure. Explanation of symbols of main parts 1,] 2...Ground wiring layer 2...Ground connection member 3...Package board 5...IC chip 6... ... Connection wire 7.8 ... Surface pad 10 ... Lead wire 51 ... IC pin Applicant: NEC Corporation (1 other person)

Claims (1)

【特許請求の範囲】[Claims] (1)半導体集積回路チップを搭載した絶縁性のパッケ
ージ基板と、このパッケージ基板に突出して取付けられ
前記チップの入出力ピンと接続されたリード線と、前記
リード線と接続された表面パッドを有するプリント基板
とを含む半導体集積回路実装構造であって、前記絶縁性
のパッケージ基板に埋設されこのパッケージ基板の側面
から略一様に突出して設けられた導体からなるグランド
層と、前記グランド層の突出部と前記プリント基板の表
面パッドのグランドパッドとの間を電気的に接続したグ
ランド接続部材とを含むことを特徴とする半導体集積回
路パッケージ。
(1) A printed circuit board having an insulating package substrate on which a semiconductor integrated circuit chip is mounted, a lead wire attached to the package substrate in a protruding manner and connected to the input/output pin of the chip, and a surface pad connected to the lead wire. a semiconductor integrated circuit mounting structure including a substrate, a ground layer made of a conductor embedded in the insulating package substrate and protruding substantially uniformly from a side surface of the package substrate; and a protruding portion of the ground layer. and a ground connection member that electrically connects the ground pad of the surface pad of the printed circuit board.
JP2196471A 1990-07-25 1990-07-25 Semiconductor integrated circuit mounting structure Expired - Fee Related JP2919010B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2196471A JP2919010B2 (en) 1990-07-25 1990-07-25 Semiconductor integrated circuit mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2196471A JP2919010B2 (en) 1990-07-25 1990-07-25 Semiconductor integrated circuit mounting structure

Publications (2)

Publication Number Publication Date
JPH0482252A true JPH0482252A (en) 1992-03-16
JP2919010B2 JP2919010B2 (en) 1999-07-12

Family

ID=16358358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2196471A Expired - Fee Related JP2919010B2 (en) 1990-07-25 1990-07-25 Semiconductor integrated circuit mounting structure

Country Status (1)

Country Link
JP (1) JP2919010B2 (en)

Also Published As

Publication number Publication date
JP2919010B2 (en) 1999-07-12

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