JPH0482412A - Pulse generator - Google Patents

Abstract

PURPOSE:To attain low cost and high setting accuracy by providing a pulse width control means which changes the setting data of both H and L intervals independently, respectively. CONSTITUTION:A data latch circuit 1 latches (H) and (L) interval setting data, and also, latches half clock control signals HLF1, HLF2 outputted from a microcomputer. Conforming to the control signals, signals HALF1, HALF2 are outputted from the latch circuit 1 to a half clock control circuit 5. The control circuit 5 shifts the ripple carry signal RCY1 of a counter circuit 2 by half clock by combining the signals HALF1 and HALF2, and controls the (H) and (L) intervals independently, respectively, thereby, both intervals can be set arbitrarily, and the setting accuracy of on and off duty can be heightened, and also, such processing can be performed with a small number of fundamental clocks.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates primarily to a pulse generator for obtaining a pulse width modulated output pulse signal for controlling a discharge lamp control lighting circuit.

[Prior Art] Conventionally, this type of pulse generator for obtaining a pulse width modulated output pulse signal for controlling a discharge lamp lighting circuit has been used.
A predetermined on/off duty (predetermined "H" interval, "L" interval) is determined by an internal counter that is formed using a microprocessor and is software-based by a program.
I was trying to obtain an output pulse signal.

However, in the above-mentioned conventional example, the setting accuracy of on and off duties is regulated by the machine cycle of the microprocessor.
sec, so it can be turned on with an accuracy of several μsec or less.
There is a problem in that an off-duty cannot be set, which causes a problem when the discharge lamp is used as a frequency generating concave path in a discharge lamp lighting device that lights a discharge lamp at a high frequency.

Therefore, in order to solve the above-mentioned problem, it is conceivable to use a presettable counter N (logic circuit) that counts the clock signal to obtain an output pulse signal that is pulse width modulated using hardware. However, even with counter circuits, the accuracy of setting the "H" section and "L" section is determined by the frequency of the clock signal, so in order to achieve high setting accuracy, a high frequency clock signal is required. If the frequency of the clock signal is increased, expensive circuit elements must be used, resulting in an increase in cost.

Further, a circuit using the half clock control method shown in FIG. 3 has been proposed.

This conventional circuit includes a data latch circuit 1 that latches the "H" section setting data and "L" section setting data of the output pulse signal, and a data latch circuit 1 that counts a constant cycle clock signal CLK and sets the above two section setting data alternately. It consists of a presettable counter circuit 2 and a toggle flip-flop circuit 3 which uses the ripple carry signal RCY from the counter circuit 2 as a trigger clock. By providing a pulse width modulated output pulse signal OUT from the toggle flip-flop circuit 3
It was designed to obtain

The pulse width control means is formed by a microprocessor, and the "H" section setting data and "L" section setting data outputted from the microprocessor are input to the input terminals IN and N+2 of the data latch circuit 1. , is latched by a timing signal output from the timing control circuit 4.

Here, the data latch circuit 1 receives latch signals LATCHA,
LATCH outputs the section setting data as reset data for the counter circuit 2. Further, the half clock control signal HLF from the microprocessor is also latched once and outputted as the signal HALF.

Further, the counter circuit 2 uses three 4-bit Brise/y-tuple counters to form a 12-bit counter circuit 2, and the ripple carry signal RCY of the counter circuit 2 is sent to a toggle flip-flop circuit via a half-clock control circuit 5. 3 as a trigger clock signal. The flip-flop output of this toggle flip-flop circuit 3 is connected to an output pulse signal OU via two inverters.
At the same time, the enable signals ENA and EN for reading preset data from the data latch circuit 1 are output.

Here, when the half clock control signal HALF is "H", the half clock control circuit 5 shifts the rise of the ripple carry signal RCY/) (the inversion timing of the toggle free 117017 circuit) to the right by half a clock, and the clock signal CLK It is possible to set the "H'" section and the "L" section with half-clock precision (double precision).

Further, the timing control circuit 4 outputs a latch signal LATCH.
, LATCHA, LATCH, , LTCH, clear signal CLEAR, load signal LOAD, latch signal L T
It generates CH+, tarock signal CLK and start signal 5TAR output from the above microprocessor.
T, a predetermined timing signal is output based on the section data set signal HL to control the operation timing of each circuit.

The operation of this conventional example is as follows.

-First, when the start signal 5TART output from the microprocessor rises, a system reset is performed.Next, when the "H" section setting data is determined, the section data setting signal HL rises from the microprocessor, and the latch signal LATCHA is set. 1 pulse is output and "H" section setting data is latched into data latch circuit 1.0
Next, when the "L" section setting data is determined, one pulse of the latch signal LATCH- is output at the falling edge of the section data setting signal HL, and the "L" section setting data is latched into the data latch circuit 1. , clear signal CLEAR
becomes “L”, the latch signal LTCH is outputted as one pulse, and the enable signal ENk is “H”, “
When the H" section setting data is read out and the load signal LOAD for setting the precert data to the counter circuit 2 is output, the "H" section setting data is set to the counter circuit 2. In this state, the counter circuit 2 starts counting the clock signal CLK, and the counter circuit 2 starts counting the clock signal CLK.
When all of the outputs Q1 to Q+2 become "H", a ripple carry signal RCY is output. This ripple carry signal RCY causes the enable signal E N a to
``H'', and at the same time the output pulse signal 0UTt, ``H''
", then the "L" interval setting data is preset in the counter circuit 2, and counting of the clock signal CLK shown in FIG. 4(a) is started. When the ripple carry signal RCY is obtained, the output pulse signal is At the same time that the enable signal ENA becomes "L", the enable signal ENA becomes "H", and the above-described operation is repeated.

Therefore, the "H" section and "L" section of the output pulse signal OUT can be set arbitrarily (12
(within a range of bits), and the on/off duty can be set.

Next, the half clock control signal HLF (that is, the data latch circuit 1
When the signal HALF) output from the ripple carry signal RCY is "L", the ripple carry signal RCY becomes the trigger clock of the toggle flip-flop circuit 3, and the output pulse signal O is synchronized with the rise of the ripple carry signal RCY.
An inversion of the UT is performed. On the other hand, when the half clock control signal HLF becomes "H", the rising edge of the ripple carry signal RCY is shifted to the right by half a clock, as shown in FIG. 4(b), and this shifted ripple carry signal RCY is toggled. This serves as a trigger clock for the float circuit 3 and performs an inversion operation of the output pulse signal OUT. Therefore, when the half clock control signal HLF is "H", the "H" interval or the "L" interval is set by half the clock signal CLK compared to the case where the interval setting data is set, as shown in Fig. 4 (c). ), the setting accuracy of the "H" section and "L" section can be doubled without increasing the frequency of the clock signal CLK.
Since inexpensive circuit elements can be used, costs can be reduced. Another feature is that by synchronizing the half clock control signal HLF with the section data setting signal HL, half clock control can be performed automatically.

[Problems to be Solved by the Invention] However, in the conventional example shown in FIG. 3, if the cycle is constant, if the on-duty is shifted by half a clock, the off-duty will be shifted by half a clock.If there is a condition where the off-duty is desired to be constant, However, there was a major drawback in that the off-duty was erratic.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a pulse generator that can achieve double the setting accuracy of on and off duty and reduce cost. .

[Means for Solving the Problems] The pulse generator of the present invention includes a data latch circuit that latches "H" section setting data and "L" section setting data of an output pulse signal, and a data latch circuit that counts a clock signal of a constant period. Consists of a presettable counter circuit in which the above two interval setting data are set alternately, and a toggle flip-flop circuit which uses the ripple carry signal from the above counter circuit as a trigger clock signal, and changes both interval setting data independently. The pulse generator is configured to obtain a pulse width modulated output pulse signal from the toggle flip-flop circuit by providing a pulse width control means for controlling the ripple carry signal by a combination of 2-bit half clock control signals. A half clock control circuit is provided which appropriately shifts the rising edge of the clock by half a clock to form a trigger clock signal.

[Function] The present invention is configured as described above, and unlike the case where the "H" interval and the "L" interval are set using the internal counter of the microprocessor, it is possible to turn on the machine cycle of the microprocessor. , the off-duty setting accuracy is not restricted and is set to “H” regardless of the machine cycle.
The section and the "L" section can be set arbitrarily, making it possible to increase the accuracy of setting the on and off duties. In addition, a half-clock control circuit is provided that appropriately shifts the rising edge of the ripple carry signal by half a clock to form a trigger clock signal in combination with the 2-bit half-clock control signal. By combining, four types of pulse width modulated output waveforms can be obtained, and half clock control of on-duty and off-duty can be performed independently.

[Embodiment] The first section shows a specific circuit of an embodiment of the present invention. In this embodiment, the data latch circuit 1 latches 8-bit "H" section setting data and "L" section setting data, and The half clock control signals HLF and HLF2 output from the microcomputer are latched, and the latched half clock control signals HLF
,,corresponding to HL F y, the signal HALF,,HALF
, from the data latch circuit 1 to the half clock control circuit 5
It is designed to output to. The half clock control circuit 5 converts the ripple carry signal RCY of the counter circuit 2 into the above-mentioned signal HALF1. By combining HALF2, it is possible to shift by half a clock and independently control the "H" period and "L" period with half a clock accuracy of the clock signal CLK, which is different from the conventional circuit. However, the operations of the timing control circuit 4, data latch circuit 1, and counter circuit 2 are basically the same as in the conventional example.

Next, the operation of the half clock control signal, which is the main part of the present invention, will be explained.
+, HA L F 2) In the case of force L”,
The ripple carry signal RCY of the counter circuit 2 directly becomes the ripple carry signal RCY which becomes the trigger clock of the toggle flip-flop circuit 3, and the output pulse signal OUT is inverted in synchronization with the rise of this ripple carry signal RCY. .

In this case, the on-duty and off-duty output pulse signal OUT having a pulse width of, for example, five pulses with respect to the clock signal CLK shown in FIG. 2(a) is the ripple carry signal RCY (RCY,) shown in FIG. 2(b). It is output as shown in FIG. 2(c) in synchronization with . On the other hand, when the half clock control signal HLFHLF2 becomes "L" or "H",
In other words, when the signals HALF, HALF2 become "L" or "H", the on-duty width is set to 5 of the clock signal CLK.
．． The ripple carry signal RCY corresponding to the falling edge of the on-duty is shifted to the right by half a clock as shown in FIG. This is used as a trigger clock for the toggle flip-flop circuit 3.

Therefore, as shown in FIG. 2(e), the width of the "H" section becomes 5.5 times of the clock signal CLK, and the width of the clock signal
The clock signal CLK can be widened by half a clock of LK.
"H" section and "L" without increasing the frequency of
The accuracy of interval setting can be doubled.

Also, half clock control signals HLF, , HLF.

When becomes “H” or “L”, that is, the signal HALFHAL
When F2 becomes "H" or "L", the ripple carry corresponding to the rising edge of the on-duty is set so that the width of the on-duty is 5 times of the clock signal CLK and the width of the off-duty is 5.5 times as above. The signal RCY is shifted to the right by half a clock as shown in FIG.

Therefore, as shown in FIG. 2(g), the "L" section has a width of 5.5 times of the clock signal CLK, and the clock signal CLK
It can be made wider by half a lock.

Furthermore, half clock control signals HLF, HL F
2 becomes “H”, “H”, that is, the signal HALF,
When HALF2 becomes "H", "H", the ripple carry signal RCY corresponding to the falling edge of the on-duty and the rising edge of the off-duty is set so that the width of the on-duty and the width of the off-duty are both 5 degrees. As shown in (h), it is shifted to the right by half a clock and is used as the trigger clock for the toggle 79117071 circuit 3.

Therefore, as shown in FIG. 2(i), the "L" and H sections have a width of 5.5 times of the clock signal CLK, and the "L"
And compared to the case where it is set by "H" section setting data, it can be made wider by half a lock of the clock signal CLK.

C Effects of the Invention] The present invention is configured as described above. The setting accuracy of on and off duty is not restricted by the microprocessor's machine cycle, as in the case of
”The interval can be set arbitrarily, the on/off duty can be set with high accuracy, and the rising edge of the ripple carry signal can be appropriately shifted by half a clock using a combination of 2-bit half clock control signals to trigger the trigger. Since a half-clock control circuit is provided to form the clock signal, four types of pulse width modulated output waveforms can be obtained by combining the 2-bit half-clock control signals, and the on-duty and off-duty can be independently controlled by the half clock. As a result, it is possible to perform fine lock control without causing fluctuations as in the conventional method, and moreover, it is possible to use half the basic clock as in the conventional method.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the same operation, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is an explanatory diagram of the same operation. 1 is a data latch circuit, 2 is a counter circuit, 3 is a toggle flip-flop circuit, 4 is a timing control circuit, and 5 is a half clock control circuit. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] (1) "H" section setting data of output pulse signal and "
a data latch circuit that latches L” section setting data;
It consists of a presettable counter circuit that counts a constant cycle clock and sets the data for setting both the above sections alternately, and a toggle flip-flop circuit that uses the ripple carry signal from the counter circuit as a trigger clock. The pulse generator is configured to obtain a pulse width modulated output pulse signal from the toggle flip-flop circuit by providing a pulse width control means for independently varying the data, and the pulse generator is configured to provide a pulse width modulated output pulse signal from the toggle flip-flop circuit. A pulse generator comprising a half clock control circuit that appropriately shifts the rising edge of a ripple carry signal by half a clock in combination to form a trigger clock signal.