JPH0482418A - Nrz data demodulator - Google Patents

Abstract

PURPOSE:To accurately perform the waveform shaping of an input signal by holding the charge voltage of an integration circuit corresponding to the detection output of a synchronous signal period to take synchronism with NRZ data. CONSTITUTION:When level-compared output is decoded by a decoder 5 at a comparator 3, and the continuation of 0 and 1 for nine bits is detected, and it is discriminated that a period is the synchronous signal period, switches 6 and 7 are opened. The operation of a V/I conversion circuit 1 is stopped corresponding to the opening of the switch 6. Also, impedance observing the output side of the V/I conversion circuit 1 from a capacitor 2 goes to high corresponding to the opening of the switch 7, and discharge is stopped. Therefore, a charge voltage is held with the capacitor 2 as it is, and accurate discrimination output can be obtained by holding the voltage during the period of data transmission. Therefore, it is possible to accurately perform the waveform shaping of the input signal.

Description

[Detailed description of the invention] (a) Industrial application field The present invention is applicable to N
The present invention relates to an NRZ data demodulator used in a system that transmits data using RZ codes.

(b) Conventional technology A receiving device that receives NRZ-encoded data as described in "Mobile Communication Story," page 51, published by Nikkan Kogyo Shimbun on May 30, 1985. is known. Fig. 3 shows such an NRZ data demodulator, which includes a high frequency amplification block (31), a frequency conversion block (32), an intermediate frequency amplification block (33),
It consists of an FM detection block (34), a low-pass filter (35), a waveform shaping circuit (36), and a CPU (37), and the CPU (37) discriminates the output pulse width of the waveform shaping circuit (36). Control, call, or display the receive block based on the demodulation and demodulation signal.

In the NRZ data receiving device configured as described above, F
The DC level of the detection output of the M detection block (34) fluctuates. In FSX demodulation, in which demodulation is performed by pulse width discrimination, since a DC level exists, faithful demodulation cannot be performed by a waveform shaping circuit that simply compares the detected output with a zero potential. Therefore, a waveform shaping circuit as shown in FIG. 4 is generally used.

Referring to Fig. 4, the FM detection signal Vdet has been input to the terminal (41) via the low-pass filter (35> in Fig. 3). A time constant circuit consisting of a resistor R1□ and a capacitor C41 is connected between the input terminals.The time constant of this circuit can be set relatively large because the frequency of the signal handled is several hundred Hz. A resistor R having the same resistance value as the resistor R41 is connected between the terminal (41) and the inverting input terminal of the comparator (42>).
4ff1 is completely connected and offset is prevented. Furthermore, the power supply terminal of the comparator (42) is grounded via the control transistor Q41, and a battery save signal (hereinafter simply referred to as a control signal) which is intermittently at a high level is applied to the base of the control transistor Q41. By inputting , the waveform shaping circuit operates intermittently to reduce power consumption. Note that this control signal VIS is NRZ
Other blocks of the data receiving system are also supplied.

The operation of the above-mentioned waveform shaping circuit will be explained with reference to FIG. The control signal Vli is an intermittent signal that is at a high level during periods ■ and I and is at a low level during a period ■, and the control signal vm
When s becomes high level, the comparator (42) becomes operational and other blocks also start operating, and the FM detection signal Vdet is input to the terminal (41>).Then, from the rise of the control signal vBs, approximately τ (= Ca, R41) During the period ■ where time elapses, the time constant circuit detects the FM detection signal Vde.
The average value Vav of t is input to the non-inverting input terminal of the comparator (42). The period ■ ends and the control signal ■. During the period (3) in which the signal is at a low level, the charge in the capacitor C41 of the time constant circuit is discharged via the resistor R41 and the low-pass filter (35).

Therefore, the comparator (42) performs accurate waveform shaping only during period (3) of each cycle in which the control signal V0 is at a high level. Note that the waveform of the FM detection signal Vdet in the figure corresponds to one modulated at a single level.

Further, the amplitude of each waveform is arbitrarily scaled.

(c) Problems to be solved by the invention By the way, the charging voltage of capacitor C41 in Fig. 4 is the average DC voltage of the input signal during normal operation, which makes accurate discrimination possible. . This is based on the assumption that the input signal itself has almost no DC component.

However, in reality, the input signal may have a DC component, and in that case, there is a problem in that the circuit shown in FIG. 4 cannot perform accurate discrimination. An input signal has a DC component when signs of the same polarity are continuous, for example '
11000001111'' where 0s and 1s are consecutive. When O and 1 are applied to the waveform shaping circuit of FIG. 4 in succession many times in this way, the capacitor C41
The charging voltage is biased towards a value corresponding to 0 or 1, causing misjudgment. FIG. 2 shows the signal configuration of the pager.

As is clear from FIG. 2, there is no problem since 0 and 1 are repeated during the bit synchronization signal period, but 0 and 1 may continue three times during the frame synchronization signal period, which poses a problem.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes an integrating circuit that detects the average DC voltage of detected NRZ data, and an integration circuit that detects the average DC voltage of the detected NRZ data and the output of the integrating circuit. a comparator circuit that compares voltage with a voltage, a memory that generates stored data in response to a call signal, and a decoder that decodes an output signal of the comparison circuit and applies a call signal to the memory in accordance with the dehood output. In the NRZ data demodulation device, a holding means is provided to hold the electric charge of the capacitor of the integrating circuit, and when the dehooder detects that a synchronization signal period for synchronizing the NRZ data has arrived,
It is characterized in that the holding means is operated in accordance with the detection output.

(*) Effect According to the present invention, when the decoder detects that the incoming NRZ data has entered the synchronization signal period for synchronizing, the charging voltage of the integrating circuit is held according to the detection output. Therefore, accurate discrimination can be made even if data with a DC component is subsequently applied.

(v) Embodiment FIG. 1 shows an embodiment of the present invention, in which (1) shows the V/I (
voltage-current) conversion circuit; (2) is the V/I conversion circuit (
(1) Integrating capacitor that charges the output current of (3)
is a comparison circuit, (4) is a ROM (read only memory) that generates stored data in response to a call signal, (
5) is a decoder that decodes the output signal of the comparator circuit (3) and applies a call signal to the ROM (4>) according to the decoded output; (6) and (7) are the detection units of the decoder (5); These are first and second switches that open and close depending on the output.

In FIG. 1, circuit elements that are the same as those in FIG. 3 are denoted by the same reference numerals, and explanations thereof will be omitted.

In FIG. 1, the pager signal as shown in FIG.
After the wave is detected by the M detection block (34) and unnecessary components are removed by the low-pass filter (35), the ■/I conversion circuit (
1) and the comparator circuit (3) are fully applied. First, during the bit synchronization signal period, the levels 0 and 1 are repeated in sequence, and the current corresponding to the repetition is applied to the V/I conversion circuit (1
) flows to the capacitor (2). Note that in the initial state, the first and second switches (6) and (7) are closed. With the opening of the first switch (6), the transistor (
8) is on, and the V/I conversion circuit (1) is operating. Therefore, since the capacitor (2) is charged with the average level (1/2) of the above 0 and 1, the output terminal of the comparator circuit (3) receives an output (waveform shaping output) whose levels have been accurately compared. can get. Here, when the output is applied to the decoder (5), the decoder (5) decodes it,
It is detected that 9 bits of 0 and 1 continue, and it is determined that it is a bit synchronization signal period. Then, the decoder (5) opens the first and second switches (6) and (7). In response to opening of the first switch (6), the transistor (8) is turned off and the V/I conversion circuit (1) stops operating. Furthermore, when the second switch (7) is opened, the impedance seen from the capacitor (2) to the output side of the V/I conversion circuit (1) becomes very large, thereby preventing discharge. Therefore, the aforementioned charging voltage is maintained in the capacitor (2) as it is. When the bit synchronization signal period ends, a frame synchronization signal period and a group designation signal period follow, followed by data of the content desired to be transmitted, but the capacitor (2) holds the above-mentioned voltage during this period. Therefore, an accurate discrimination output appears at the output end of the comparison circuit (3). As a result, you can output the message, etc. you want to display to the output terminal (
9〉 can be obtained. When the content to be transmitted ends, the decoder (5>) detects that the content has ended.
According to the detection output, the first and second switches (6) and (7) are closed to return to the initial state. By doing so, it enters the waiting state for the next reception.

Furthermore, when the second switch (7) is open, the capacitor (
2) has a slight discharge (generally due to the base current of the transistor) to the non-inverting input terminal (+) of the comparator circuit (3), but it is very small and it is sufficient to hold it for several tens of seconds. possible.

(g) Effects of the Invention As described above, according to the present invention, it is possible to provide an NRZ data demodulation device that can accurately shape the waveform of an input signal.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a signal configuration diagram of pages ~, Fig. 3 is a block diagram of an NRZ data receiving system, and Fig. 4 is a circuit diagram of a conventional waveform shaping circuit. 5 and 5 are waveform diagrams for explaining FIG. 4.

Claims (2)

[Claims] (1) An integrating circuit that detects the average DC voltage of the detected NRZ data, a comparison circuit that compares the NRZ data and the output voltage of the integrating circuit, and generates stored data in response to a call signal. An NRZ data demodulator comprising: a memory; and a decoder that decodes an output signal of the comparator circuit and applies a call signal to the memory in accordance with the decoded output, the retention means for retaining the charge of the capacitor of the integration circuit. NRZ data demodulation device, wherein when the decoder detects that a synchronization signal period for synchronizing NRZ data has arrived, the holding means is operated in accordance with the detection output. (2) The NRZ data demodulator is characterized in that the synchronization signal period is a bit synchronization signal period that does not include a DC component.