JPH0482444A - serial interface - Google Patents

Abstract

PURPOSE:To easily detect the error of a signal and to display it as an error flag by extracting a period which is assumed as the error as the pulse period of an error detection permission signal when the fluctuation of a data occurs. CONSTITUTION:An edge detection circuit 11 detects level change generated in a shift clock 14 after passing a buffer 6, and outputs an edge detection signal 15. When the signal 15 is generated in the pulse period when the error permission signal represents a permission state, the information of the fact is held with the error flag 12, and the fact that a noise is generated in the shift clock and the mis-shift of data occurs is displayed. Thereby, the presence/absence of the error in a reception signal can be easily detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a serial interface circuit that serially transmits data based on a clock having a constant period.

2. Description of the Related Art In recent years, single-chip microcomputers have become highly integrated and highly functional, and as the proportion of a single control microcomputer being involved in the application equipment has increased, serial interfaces have become increasingly popular for exchanging data with peripheral devices. It has become essential to use When exchanging data via this serial interface, it is important for the microcomputer application equipment to operate normally to check whether the transmitting side or the receiving side can correctly receive the transmitted data.

Conventionally, this type of circuit has had a configuration as shown in FIG.

As shown in Figure 6, the components are: 1 is a central processing unit (hereinafter referred to as CPU) that exchanges n-bit data with the outside as serial data, and 2 is a central processing unit (hereinafter referred to as CPU) that converts n-bit parallel data into serial data. A shift register for sending out one bit at a time or converting serially received n-bit data into parallel; 3 is a counter for generating a soft clock for shift register 2; 4 is a shift clock generated by counter 3; , 5 is a data transmission buffer for transmitting serial data sent from the /button register 2 to a long distance, 6 is a clock transmission buffer for transmitting a shift clock to a long distance, 7 is a serial reception data received from a long distance, 8 is data A transmitting terminal, 9 is a clock transmitting terminal, and 10 is a data receiving terminal.

Regarding the serial interface configured as shown in FIG. 6, the relative operations of its constituent elements will be explained below. In order to serially transmit n-bit data using the circuit shown in FIG. 6, first transfer and store n-bit parallel data from the CPUI to the shift register 2. Next, the counter 3 generates a pulse with a constant period, and this is used as the shift clock 4 to cause the n-bit data to be shifted into the stored shift register 2. As described above, the transmission data that has passed through the data transmission buffer 5 is transmitted from the data transmission terminal 8, the shift clock that has passed through the clock transmission F buffer 6, or the clock transmission terminal 9.

The operation on the transmitting side has been explained above, and the operation on the receiving side will also be briefly explained.

When receiving data using the start-stop synchronization method, input the transmitted serial data from the data receiving terminal 10 shown in FIG. The n-bit data is stored in the shift register 2 by generating it by operating the counter 3 at a period agreed upon in advance with the transmitting side. At this point, the reception-side CPUI takes in n-bit data from the shift register 2, thereby completing the asynchronous data reception.

Next, when receiving in a clock synchronous manner, input the transmitted serial data from the data reception terminal 10 in FIG. By inputting a shift clock not shown in FIG. 6 or sent from the transmitting side from the clock receiving terminal, n-bit data is stored in the shift register 2. At this point, the receiving side's CP
When the UI takes in n-bit data from the shift register 2, the clock-synchronous data reception is completed.

Problems to be Solved by the Invention However, with the above configuration, if noise synchronized with the shift timing of the shift register 2 on the receiving side is added to the data sent from the transmitting side, that is, if a level fluctuation occurs due to some external factor. In some cases, part or all of the correct n-bit data that should have been transmitted may be incorrectly transmitted, or in the case of a clock synchronous system, noise may be added to the shift clock transmission line. In this case, there is a possibility that shift register 2 will be shifted at the wrong timing on the receiving side, so it is necessary to run the CPUI to check whether the n-bit data has been received correctly. However, there has been a problem in that it increases the burden on software programming and further reduces the processing capacity of the CPUI. For example, after completing the transmission of n bits of data, the receiving side sends the received n bits of data back to the transmitting side, so that the transmitting side can check the data and compare it with the data that was originally scheduled to be transmitted. After or before continuously transmitting m sets of n-bit data, by transmitting data (for example, a checksum) that is uniquely determined from the mu data, the receiving side can independently calculate the actual value from the m sets of data. There is a method of calculating and checking the uniquely determined data, but in both of the above methods, errors may occur during transmission and reception depending on how noise is affected when transmitting data and when transmitting check data. may not be detected.

The present invention has been made with the above-mentioned problems in mind, and an object of the present invention is to provide a serial interface that can detect errors that occur during transmission and reception while minimizing the burden on the CPU.

Means for Solving the Problems In order to achieve the above object of the present invention, a counter is provided which generates an error detection enable signal whose pulse output is a period excluding at least a level fluctuation period for each cycle of a soft clock or a shift clock. , is provided with a transmission/reception shift clock or an edge detection circuit for detecting level fluctuations in transmission/reception data between pulses IA of this error detection permission signal, and when a level fluctuation is detected by the edge detection circuit,
This is a serial interface configuration in which an error flag indicates that an error has been detected.

The serial interface of the present invention having the above configuration is synchronized with the soft clock, and extracts the period considered to be an error when there is a data level fluctuation as the pulse period of the error detection enable signal, so it can be used without placing much load on the CPU. , an edge detection circuit can easily detect errors in the signal. Then, an error message is definitely displayed using an error flag.

Embodiment FIG. 1 shows the configuration of a serial interface according to an embodiment of the present invention. As shown in Figure 1, as a component 1
2 is a CPU that converts n-bit parallel data into serial data and controls the exchange with the outside, 3 is a counter having a first clock terminal that outputs a shift clock of the shift register with a period of 2T, and a second clock terminal that outputs an error detection permission signal with a duration of T-ΔT. , 4 is a shift clock output from the first clock terminal of the counter 3, 5 is a data transmission buffer for transmitting the serial data sent out from the shift register 2 to a long distance, and 6 is a shift clock for transmitting the shift clock to a long distance. Clock transmission buffer, 7 is serial reception data received from a distance, 8 is data transmission terminal,
9. is a clock transmission terminal, 10 is a data reception terminal, 11
is the shift clock transmitted from the clock transmission terminal 9,
In other words, an edge detection circuit for detecting a change in the shift clock level received by the receiving side; 12 is an error flag for holding information "if the edge of the shift clock is detected within the error detection period; 13 is an error flag for the counter 3; Second
14 is a shift clock actually received by the receiving side after passing through the clock transmission buffer 6, and 15 is an edge detection signal.

Regarding this embodiment configured as above, the mutual relationship and operation of each component will be explained below.

The method of transmitting n bits of data using this circuit is basically the same as the method explained in the conventional example, so here we will explain how to detect errors in communication when transmitting n bits of data using this circuit. I will explain only the bamboo shoots.

FIG. 1 shows a circuit configuration in the case of a clock synchronous type, in which a shift clock used for data transmission of n bits is generated by a counter 3. Here, the cycle of the shift clock is 2T and the duty is 50%. Here, the counter 3 which generates the time interval T also outputs an error detection permission signal excluding the rising and falling portions of the shift clock with a duration T-ΔT. In general, if you have a counter with the number of bits required to generate a period of T, then
Since it is possible to create a time interval of -ΔT by using some of the bits, the rise of the shift clock,
T-ΔT from the second clock terminal of the counter 3 excluding at least the falling part, that is, the part with level fluctuation.
It is not difficult to generate a pulse of the error detection enable signal.

Next, there is an edge detection circuit 11 that is unique to this embodiment. This is to detect the level change of the shift clock with a period of 2T generated from the first clock terminal of the counter 3, or what is important here is to detect the level change on the output side of the clock transmission buffer 6. It is a point.

The shift clock 4 before passing through the buffer is the output of the counter 3 itself, and is not output to the outside of the LSI constituting this serial interface, so it is difficult for noise to be added to the shift clock 4. Rather, the LS is passed through the clock transmission buffer 6 and the clock transmission terminal 9.
After I is output to the outside, there is a high possibility that a level change will occur due to the influence of noise, and the purpose is to detect this, so edge detection is performed directly from the clock transmission terminal 9 as shown in Figure 1. It is important to route the shift clock to circuit 11. Therefore, this edge detection circuit 11 is connected to the buffer 6.
A level change occurring in the shift clock 14 after passing is detected and an edge detection signal 15 is output. If this edge detection signal 15 or the error detection permission signal is generated during the pulse period indicating the permission state, the error flag 12 holds information to that effect, indicating that noise has been added to the shift clock and data has been misshifted. represents.

The operation of this embodiment described above is expressed using timing charts of each signal in FIGS. 2 and 3. Figure 2 shows the case where all 2 bits of data are transmitted without a shift error, and Figure 3 shows that when transmitting all 2 bits of data, a shift error occurs due to noise on the 7-foot clock, and error flag 12 is raised. This represents each case when standing.

FIG. 2 (1a) shows the output data signal of the data transmission terminal 8, FIG. 2 (bl shows the shift clock 4 output from the counter 3, and FIG.
Shift clock 14 at clock transmission terminal 9 is shown. FIG. 2 1d) shows an edge detection signal 15 obtained by detecting the level fluctuation of the shift clock 14 by the edge detection circuit 11.
The error detection enable signal 13 has a pulse output for a period excluding the level fluctuation portion of the signal, that is, the edge detection signal 15 in this case. In FIG. 2, since there is no level fluctuation of the shift clock 14 within the pulse period of the error detection permission signal 13, there is no output of the error flag 12 in FIG.

FIG. 3 shows a third shift clock 14 in FIG. 3 fcl.
Since there is a level fluctuation in the pulse period of the error detection permission signal 13 in Figure tel, the edge detection signal 15 in Figure 3 fdl
The output of the error flag 12 in FIG. 3 (fl) changes to high level from then on, indicating that an error has occurred.

As described above, according to the present invention, it is possible to detect that a shift error has occurred on the receiving side due to noise on the shift clock on the transmitting side without sending data back from the receiving side or calculating a checksum on the receiving side. Can be detected.

Although FIGS. 1 to 3 describe an embodiment in which the present invention is applied to the shift clock terminal of a clock-synchronous serial interface, in FIG. Transmission data 8 is input, and the error detection permission signal output from counter 3 is changed from T-ΔT to 2T-ΔT.

In other words, a circuit configuration for easily detecting noise on the data signal line of an asynchronous serial interface is created by configuring the pulse output, excluding the level fluctuation part for each period of the shift clock 4. You can take it. The timing chart of each signal in that case is shown in the fourth section.
As shown in FIG. Figure 4 shows the case where all 2 bits of data are transmitted without error using the asynchronous method.
FIG. 5 shows a case where error flag 12 is raised due to noise on the data signal line during data transmission of all 2 bits using the asynchronous method.

FIG. 4 fat is the data of the data transmission terminal 8;
Data is output every 2T timing of one cycle of shift clock 4 in FIG. fbl. FIG. 4 (C1 is an edge detection signal 15 from the edge detection circuit 11, which detects level fluctuations in data cycles of 2T, which corresponds to level fluctuations in each cycle of the shift clock 4. FIG. 4 fdl shows the error detection permission signal 13 from the counter 3 having a pulse output excluding at least the level fluctuation part. Detection circuit 11
It shows the output of the error flag 12 which indicates an error when a level change is detected by the above, and in this case, there is no level change, so there is no signal. FIG. 5 shows a case where there is a level fluctuation of the data at the data transmission terminal 8 shown in FIG. 5(a), and the output of the error flag 12 of tel in FIG. 5 is output as an error display signal.

Although the above description has been made regarding error detection on the transmitting side, it goes without saying that error detection of received signals can be similarly performed by synchronizing the shift clock.

Effects of the Invention As is clear from the above explanation, there is provided a counter that generates an error detection permission signal having a pulse output for a period excluding at least a shift clock or a level fluctuation period for each period of the shift clock, and a counter for generating an error detection permission signal. Equipped with an edge detection circuit that detects transmission/reception/crossovers or level fluctuations in the transmission/reception data during the pulse period, and when level fluctuations are detected, an error flag is displayed indicating that an error has been detected, thereby detecting errors in the transmitted signal on the transmitting side. This is a serial interface that allows you to check in advance whether there is an error in the received signal and easily detect the presence or absence of an error in the received signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a serial interface according to an embodiment of the present invention, FIGS. 2 and 3 are timing charts when the same embodiment is applied to a clock-synchronous serial interface, and FIG. 4 and FIG. 5 are timing charts when applied to the asynchronous serial interface of the same embodiment, and FIG.
The figure is a block diagram showing the configuration of a conventional serial interface. 1...CPU, 2...Shift register, 3...Counter, 5...Data transmission buffer, 6...Clock transmission buffer, 8・
...Data transmission terminal, 911813. Clock transmission terminal, 10...Data reception terminal, 11...
...Edge detection circuit, 12...Error flag. Name of agent: Patent attorney Shigetaka Awano Haka 1 (6) Error 7? -= Shift Resuta Data'' I8 Buffalo Cloth/Futsushin Hub 77 Child-Fu, Send-I L Aging Child Kuro, Tsuku Tono T is condyle and (α) Datum 14 Cicada 5 (b) Shi7 Tokuro , riT Error flux (α) Chee - ri passing error 1 left <b) Shift clock

Claims (2)

[Claims] (1) A shift register for converting parallel data into serial data and sending it out one bit at a time, and for converting serial data received in series into parallel data, and a first clock terminal for generating a shift clock for the shift register; , a counter having a second clock terminal that generates an error detection enable signal whose pulse output is a period excluding at least a period of level fluctuation of the shift clock, and a clock output terminal that receives the shift clock from the counter as an input and outputs an output. an edge detection circuit that detects level fluctuations at the output terminal of the clock, an error flag that displays an error in the shift clock at the output terminal of the clock, and controls the exchange of the data and shift clock signals. and a central processing unit, when the edge detection circuit detects a level fluctuation during the pulse period of the error detection permission signal by the central processing unit, an indication that an error has been detected is displayed on the error flag. Serial interface that becomes implemented. (2) a shift register for converting parallel data into serial data and sending it out one bit at a time, and for converting serial data received in series into parallel data; and a first clock terminal for generating a shift clock for the shift register; , a counter having a second clock terminal that generates an error detection enable signal whose pulse output is a period excluding at least a level fluctuation period for each cycle of the shift clock, and inputting the output serial data of the shift register, a buffer whose output is connected to a data output terminal; an edge detection circuit that detects level fluctuations at the data output terminal; and an error flag that indicates an error in data at the data output terminal;
and a central processing unit that controls the exchange of the data and shift clock signals, and the central processing unit controls, during the pulse period of the error detection permission signal,
In the serial interface, when the edge detection circuit detects a level fluctuation, an indication that an error has been detected is displayed on the error flag.