JPH0483342A - Manufacture of semiconductor device, and semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the silicide compound of a high melting point metal from entering into the inside of a semiconductor substrate by selectively implanting silicon ion in at least a part of a high melting point metal layer formed on a conductive layer. CONSTITUTION:Ti layer 7 of 40nm is formed as a high melting point metal layer. A photoresist layer is formed on this Ti layer 7 and processed into a resist pattern 8. Further, Si ion 9 is implanted in the Ti layer 7 by using the pattern 8 as a mask. Then, after the resist pattern 8 has been removed, the Ti layer 7 and the implanted Si ion are caused to react with each other by heat treatment so that Ti silicide layers 10a, 10b are respectively formed on a source 3a and drain 3b in the manner of ranging over a field oxide film 2 and a gate side wall 6. In this case, a Ti silicide layer 10c is formed also on a gate electrode 5. There occurs no such trouble that the Ti layer 7 reacts with the source 3a and drain 3b and accordingly the Ti silicide layers 10a, 10b enter deeply the source 3a and drain 3b respectively.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and in particular to a method for manufacturing a semiconductor device using a silicide compound of a high melting point metal in a wiring layer. The present invention relates to an improved method and the semiconductor device.

(Prior Art) Recent advances in semiconductor process technology have been remarkable, and along with this, research and development has been actively conducted on materials used in semiconductor devices. Currently, it is generally necessary to form an insulating film such as PSG (phosphosilicate glass) on wiring and the like in order to reduce the level difference in semiconductor elements and to protect semiconductor elements from contaminants. However, the process of forming an insulating film such as PSG requires a high temperature of about 900°C, and there was a problem that Al2 or its alloys, which are currently commonly used for wiring, have a melting point lower than the above temperature and are difficult to use. .

Therefore, attention is being paid to the use of high-melting point metal silicide compounds with high melting points and good electrical conductivity for wiring.

Conventionally, a method using amorphous Si is known as a method for forming a wiring layer of this high melting point metal silicide compound. FIG. 5 is a process sectional view showing a conventional method of forming a wiring layer made of a high melting point metal silicide compound using amorphous Si.

First, after selectively forming a field oxide film 52 for element isolation on the surface of the Si substrate 51, this field oxide film 52 is
Source 53a1 drain 5 is placed in the element formation region surrounded by
3b, a gate insulating film (oxide film) 54 is formed on the channel 53c between the source and the drain, a gate electrode 55 made of polycrystalline silicon is formed thereon, and the gate oxide film 54 and the gate electrode 55 are formed. Gate side walls 56 are formed on the sides.

Next, as shown in FIG. 5(a), a high melting point metal layer 57 is formed on the entire surface, and an amorphous Si layer is further formed thereon.

Next, a photoresist layer is formed on the amorphous Si layer 58,
This photoresist layer is processed by photolithography to match the wiring shape to form a resist pattern 59 (FIG. 5(b)).

Next, as shown in FIG. 5(e), the resist pattern 5 is
After selectively removing the amorphous Si layer 58 using 9 as a mask, the resist pattern 59 is removed.

Next, the amorphous Si layer 58 and the high melting point metal layer 57 are caused to react by heat treatment, and the high melting point metal silicide compound layer 81)
A and 60b are formed on the source 53a and drain 58b, respectively (FIG. 5(d)). At this time, the gate electrode 55
A refractory metal silicide layer BoC is also formed thereon. Further, the unreacted amorphous Si layer 58a is placed on the silicide compound layer Baa, 80b, and the unreacted high melting point metal layer 57
A remains outside the wiring formation area. Furthermore, as shown in FIG. 5(e), this unreacted amorphous St layer 58a is removed. Finally, after shaping the interlayer insulating film 61 over the entire surface, contact holes (A and B) are opened to expose Boa and 80b of the high melting point metal silicide compound layer, respectively, and the contact holes A and B are filled. wiring layers 62a and 62b, respectively.
form.

However, the above-mentioned method has two main problems.

The first problem is that the high melting point metal silicide compound layer 130
When forming layers a and 80b, the high melting point metal layer 57 is made of Si.
A reaction also occurs with the substrate 51, and as a result, the high melting point metal silicide compound layer 60a, [lOb] penetrates deeply into the source and drain diffusion layers 53a and 53b, and in extreme cases, it penetrates the source 53a and drain 53b. It ends (60d). In this case, leakage current flows into the substrate 51, causing serious situations such as increased current consumption and malfunction of elements.

The second problem is that the high melting point metal silicide compound layer BOa,
After forming the interlayer insulating film 60b, when heat treatment is performed to form the interlayer insulating film 61, oxygen contained in the amorphous Si layer 58 melts into the high melting point metal silicide compound layer 80a.

This is because it promotes aggregation of 60b, for example 60e. When this aggregation occurs, wiring resistance increases locally and the characteristics of the element deteriorate.

The above-mentioned problems apply to all semiconductor devices formed on semiconductor substrates, particularly silicon substrates, and a serious situation has arisen in which the reliability of the semiconductor devices is reduced.

(Problems to be Solved by the Invention) As described above, the conventional method for manufacturing a semiconductor device in which a high melting point metal silicide compound wiring layer is formed using amorphous St and the semiconductor device are The compound layer may invade conductive layers, such as source and drain diffusion layers, resulting in increased current consumption and device malfunction, and oxygen contained in the amorphous Si layer may promote aggregation of the high melting point silicide compound layer. However, the reliability of the semiconductor device has been significantly reduced due to the problem that wiring resistance increases locally.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device that solve the above-mentioned problems.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention includes a step of selectively forming a conductive layer on the surface of a semiconductor substrate, and a step of forming a high melting point metal layer on the semiconductor substrate. a step of selectively implanting silicon ions into at least a portion of the high melting point metal layer formed on the conductive layer; and a step of selectively implanting silicon ions into at least a portion of the high melting point metal layer formed on the conductive layer, and a silicide compound layer of the high melting point metal in the portion into which the silicon ions are implanted by heating. Provided is a method for manufacturing a semiconductor device, comprising the steps of: forming a high-melting point metal layer; and selectively removing a remaining high-melting point metal layer.

The present invention also provides a semiconductor substrate, a conductive layer selectively formed on the surface of the semiconductor substrate, a high melting point metal layer formed on at least a portion of the conductive layer, and silicon ions being implanted into the high melting point metal layer. and a silicide compound layer of a refractory metal formed by heat treatment.

(Function) According to the method for manufacturing a semiconductor device according to the present invention, silicon ions are selectively implanted into at least a portion of the high melting point metal layer formed on the conductive layer, so that the silicon ions are implanted by heating. When attempting to form a silicide compound layer of a high-melting point metal on a high-melting point metal layer, the metal atoms in the high-melting point metal do not react with the atoms of the semiconductor substrate that exist under this high-melting point metal layer, and instead react with the silicon ions. The reaction occurs preferentially, and the silicide compound of the high melting point metal is inhibited from entering into the conductive layer or the semiconductor substrate. Therefore, there is no leakage current into the semiconductor substrate, and therefore no increase in current consumption or malfunction of the device occurs.

Further, in the step of implanting silicon, no oxygen is mixed in, so that the silicide compound layer of the high melting point metal does not aggregate, and the wiring resistance does not increase locally.

Further, in the semiconductor device according to the present invention, the refractory metal silicide compound layer is formed by forming a refractory metal layer on at least a portion of the conductive layer, implanting silicon ions into the refractory metal layer, and performing heat treatment. Therefore, a structure suitable for solving problems caused by the refractory metal compound layer penetrating into the conductive layer or semiconductor substrate or agglomeration is provided, and the reliability of the semiconductor device is improved. will improve dramatically.

(Example) Details of the method for manufacturing a semiconductor device according to the present invention and the semiconductor device according to the present invention manufactured by this method will be described below.
An example will be explained using a MOSFET as an example.

First Embodiment FIG. 1 is a process sectional view of a first embodiment of a method for manufacturing a semiconductor device according to the present invention for explaining a semiconductor device according to the present invention. First, a field oxide film 2 for element isolation is selectively formed on the surface of a p-type Si substrate 1. Next, an n-type source region 3a and a drain region 3b are formed as a conductive layer on the surface of the p-type Si substrate 1 in the element formation region.
A gate oxide film 4 and a gate electrode 5 made of n-type polycrystalline Si are placed on the channel 3c between the gate oxide film 4 and the drain 3b.
Form the O2 gate sidewall 6. (Figure 1(a)).

Next, as shown in FIG. 1(a), a Ti layer 7 with a thickness of 40 nm is formed as a high melting point metal layer over the entire surface by sputtering. A photoresist layer is formed on this Ti layer 7 and processed into a resist pattern 8. Furthermore, using this pattern 8 as a mask, Si ions 9 are deposited in the Ti layer at an acceleration voltage of 30K e V and a dose of 1 x 10" am-
Input under conditions of about 2 (Fig. 1 (C)).

Next, as shown in FIG. 1(d), after removing the resist pattern 8, the implanted Si ions are reacted with the 71 layer 7 by heat treatment at 700°C, and the Ti silicide layer 10a is made to react with the implanted Si ions.
, 10b are formed on the source 3a1 and the drain 3b, respectively, so as to extend over the field oxide film 2 and the gate sidewall 6. At this time, a Ti silicide layer 10c is also formed on the gate electrode 5. In addition, unreacted Ti layer 7a remains in areas other than the area where wiring is to be formed. Furthermore, unreacted Ti layer 7a
is removed by immersing it in an aqueous solution of hydrogen peroxide and ammonia while heating (Fig. 1(e)).

Next, SiO2 (P S G ) containing phosphorus on the entire surface
After forming layer 11, refractory metal silicide layer 10a.

Connection holes A and B are opened to expose lOb, respectively. Finally, an AI film is formed by sputtering so as to fill the contact holes A and B, and this A1 layer is patterned to form wiring layers 12a and 12b connected to the source 3a and drain 3b, respectively. Figure 1 (r)). As a result, the first embodiment of the semiconductor device according to the present invention is completed. Note that FIG. 1(g) is a top view of the apparatus of this embodiment.

In the method and apparatus of this embodiment, the 71 layers 7 are
Because it preferentially reacts with the Si ions implanted into layer 7,
71 layer 7 reacts with source 3a and drain 3b, thereby forming Ti silicide layer 10a.

There is no problem that tob penetrates deeply into the source 3a and drain 3b, respectively. In addition, when implanting Si ions, oxygen is mixed into <<, the SiO□ layer 1 containing phosphorus.
Even if heat treatment is performed in one step for a single layer type, the Ti silicide layer 10
a, 10b, and 10c do not aggregate. Furthermore, since contact is made with the source 3a and drain 3b on the field oxide film for element isolation, there is no need to take a margin for misalignment when opening the connection holes A and B, which facilitates miniaturization of the element. It is also convenient for planning purposes.

FIGS. 2 and 3 are top views showing a modification of this embodiment device. In these figures, the same parts as in FIG. 1 are denoted by the same reference numerals, and detailed explanations will be omitted. As shown in FIG. 2, the source region 3 of the Si ion refractory metal layer is
a. A part of the drain region 3b is implanted, and Ti silicide layers 21a and 21b are formed in this part.

21b may be connected to wiring layers 22a and 22b within the source region 3a and drain region 3b, respectively. Furthermore, as shown in FIG. 3, Si ions are implanted into a portion including the boundary between the field oxide film 2 and the source 3a and the boundary between the field oxide film 2a and the drain 3b, and Ti silicide layers 81a, 8 are formed in this portion.
1b may be formed respectively.

Generally, at the edges of the source and drain regions, such as between the source and drain and the field insulating film, the refractory metal silicide layer is particularly likely to invade the source and drain regions.
Even by implanting silicon ions only in this portion, the effect of preventing the invasion can be sufficiently obtained.

Second Embodiment FIG. 4 is a cross-sectional explanatory diagram showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention for explaining the semiconductor device according to the present invention. In this figure, the same parts as in FIG. 1 are designated by the same reference numerals, and detailed explanation will be omitted.

First, the element shown in FIG. 1(a) is formed on an St substrate,
On this entire surface, a 71 layer 7 with a thickness of 40 nm was applied by sputtering.
A 50 nm thick T i Nx layer 41 is formed in this order. Furthermore, a resist pattern 8 is formed thereon in the same manner as in the first embodiment, and using this resist pattern 8 as a mask, Si ions 9 in the Ti layer are accelerated at a voltage of 45 KeV.
The implantation is performed at a dose of about 1 x 1o 17clI-2 (Fig. 4(a)).

Next, as shown in FIG. 4(b), after removing the resist pattern 8 by, for example, ashing using oxygen plasma or corroding with acid, the 71 layer 7 and the implanted Si ions are removed by heat treatment at 700°C. By reacting, Ti silicide layers 10a and 10b are formed on the source 3a and drain 3b, respectively, so as to cover the field oxide film 2 and gate sidewalls 6. At this time, Ti is also applied on the gate electrode 5.
A silicide layer 10c is formed. Further, an unreacted Ti layer 7a remains outside the area where the wiring is to be formed. Furthermore, TiNx layer 4
The Ti layer 7a of the single layer type 1 layer is selectively removed using a heated aqueous solution of hydrogen peroxide and ammonia. Note that in this case, sulfuric acid may be used instead of ammonia.

Generally, when attempting to remove the resist pattern by ashing using the oxygen plasma described above, the high melting point metal layer formed thereunder may also be oxidized at the same time. Also,
When attempting to corrode and remove a resist pattern using acid, the metal layer may also be corroded at the same time. As in this example, if a TiNx layer 41 is formed as a base for the resist pattern 8, the Ti layer 7 under the TiNx layer 41 can be protected and the above problem can be completely solved. .

Next, S I Q2 (P S
G) forming layer 11 and forming Ti silicide layers 10a and 10b
Connection holes A and B are respectively opened to expose the. Finally, an Ai) layer is formed by sputtering, and this A1 layer is patterned to form wiring layers 12a and 12b that are connected to the source 3a and drain 3b, respectively (FIG. 4(e)), in this case. , the TiNx layer 41 may be left as it is and contacts with the source and drain may be made on this layer. With this embodiment method, effects similar to those of the first embodiment can be obtained, and as a result, an embodiment of the semiconductor device according to the present invention similar to the first embodiment is completed. In addition,
The present invention is not limited to the above embodiments. For example, in the above embodiment, an n-channel type MOSFE
Although we have explained the case of T, p-channel type MOSF
The same can be applied to ET. Further, the present invention
It can be applied to general methods and devices for connecting a high-melting point metal silicide layer to a diffusion layer on a semiconductor substrate. Specifically, it can be applied to FETs other than MOSFETs, such as FETJpMESFETs having a PN junction gate, or bipolar transistors. can also be applied. Furthermore,
The high melting point metal material is not limited to the above-mentioned examples, and in addition to Ti, examples include W, Mo, Ta, Co, and Ni.

Metals such as Pd or also alloys thereof can be used. Furthermore, as a method for forming the high melting point metal layer, in addition to the sputtering method, a CVD method, a vacuum evaporation method, an electrolytic or electroless plating method can be used. In addition, TiN is used as a protective film for the high melting point metal layer during resist pattern removal.
Although x is used, the present invention is not limited to this, and any material may be used as long as it has sufficient etching resistance when removing the resist pattern. For example, silicon oxide or nitride may be used. Furthermore, it goes without saying that the photoresist layer serving as a mask during Si ion implantation may be replaced with another material. The point is that it can be used as a mask for Si ion implantation. In addition, the ions to be implanted are not limited to silicon ions, and other ions such as ions of group (I) elements such as C and Ge may be used.

Furthermore, it goes without saying that various changes can be made without departing from the gist of the present invention.

[Effects of the Invention] As explained above, according to the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, the intrusion of the high melting point metal silicon side compound layer into the conductive layer or the semiconductor substrate and the aggregation of the high melting point metal silicide compound are prevented. is suppressed, and the reliability of the semiconductor device is greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a step sectional view and a top view of a first embodiment of a method for manufacturing a semiconductor device according to the present invention for explaining a semiconductor device according to the present invention, and FIGS. 2 and 3 are diagrams showing the embodiment of the present invention. FIG. 4 is a top view showing a modification of the device; FIG. 4 is a process sectional view of a second embodiment of the method for manufacturing a semiconductor device according to the present invention for explaining the semiconductor device according to the present invention; FIG. FIG. 3 is a process cross-sectional view showing a method of forming a wiring layer of a metal silicide compound. 1...p-type St substrate, 2...field oxide film, 3
a...n type source region, 3b...n type drain region, 3C...channel, 4...gate oxide film, 5
...gate electrode, 6...SiO2 gate side wall, 7.
... Ti layer, 7a... Unreacted Ti layer, 8... Resist pattern, 9... Si ion, lOa, lOb,
lOc, 21a, 21b, 31a, 31b, ---Ti
Silicide layer, 11-PSG layer, 12a, 12b,
22a. 22b... Wiring layer (Ajri A, B... Connection hole,
41...TiNx layer, 51...Si substrate, 52...
・Field oxide film, 53a... Source, 53b...
・Drain, 53C... Channel, 54... Gate insulating film (oxide film), 55... Gate electrode, 5B...
Gate side wall, 57... High melting point metal layer, 57a... Unreacted high melting point metal layer, 58... Amorphous Si layer, 58m
...Unreacted amorphous Si layer, 59...Resist pattern, 60a, 80b, 80c...High melting point metal silicide compound layer, 80d...Source 58a, drain 5
Refractory metal silicide compound layer passing through 3b, 80e
...Agglomerated portion of high melting point metal silicide compound layer, B1
. . . Interlayer insulating film, 62a, (12b . . . Wiring layer.

Claims (4)

[Claims] (1) A step of selectively forming a conductive layer on a surface of a semiconductor substrate, a step of forming a high melting point metal layer on the semiconductor substrate, and a step of forming a high melting point metal layer on at least a portion of the high melting point metal layer formed on the conductive layer. The method includes a step of selectively implanting silicon ions, a step of forming a silicide compound layer of a high melting point metal in the portion into which the silicon ions are implanted by heating, and a step of selectively removing the remaining high melting point metal layer. A method for manufacturing a semiconductor device, characterized in that: (2) Claim (1) characterized in that an insulating film for element isolation is formed around the conductive layer, and the silicide compound layer of the high melting point metal is integrally formed over the insulating film for element isolation. A method of manufacturing the semiconductor device described above. (3) After the step of forming the high melting point metal layer, forming a thin film having etching resistance on the high melting point metal layer,
A pattern is formed on the thin film to serve as a mask for use in the step of implanting silicon, and after the step of selectively implanting silicon ions, a step of etching away the pattern is performed to remove the high melting point metal. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing at least the thin film on the remaining refractory metal layer after the step of forming the silicide compound layer. (4) A semiconductor substrate, a conductive layer selectively formed on the surface of the semiconductor substrate, a high melting point metal layer formed on at least a portion of the conductive layer, silicon ions implanted into the high melting point metal layer, and heat treated. 1. A semiconductor device comprising: a silicide compound layer of a high melting point metal formed by performing the above steps.