JPH0483346A - Bipolar transistor and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bipolar transistor and a method for manufacturing the same.

(Prior Art) Bipolar transistors have an excellent feature of higher current driving ability than field effect transistors. Therefore, in recent years, research and development of bipolar transistors using not only Si but also compound semiconductors such as GaAs have been actively conducted. In particular, bipolar transistors using compound semiconductors have significant advantages, such as being able to configure the emitter-base junction into a heterojunction, and maintaining high emitter injection efficiency even when the base is highly doped.

FIG. 3 is a cross-sectional view of a semiconductor chip for explaining the structure of a conventional bipolar transistor.

This semiconductor chip consists of a semi-insulating substrate 1 made of GaAs.
, a collector layer 3 made of n-GaAs, and a p-G
A base layer 4 made of aAs, n ”0.25GaO,
It is composed of an emitter layer 5 made of 75As, an emitter electrode 9 made of AuGeNi, a base electrode 18 made of AuZnNi, and a collector electrode 11 made of AuGeNi.

Typically, the base layer has a thickness of 70 to 1100 nm and a p-type impurity concentration of 10 nm to operate the transistor at high speed.
It is often set in the cm range. As the p-type pure dopant, Be is often used, for example, when forming a base layer by a molecular beam epitaxy method (hereinafter referred to as MBE method). In Fig. 3, the emitter and base junctions are of a stepped junction type, but in addition to this, the AlxGa1-xAs emitter layer has a
A gradient junction type in which the composition X is gradually changed is also often used.

FIGS. 4A to 4C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the above-mentioned conventional method for manufacturing a bipolar transistor.

In this conventional example, first, as shown in FIG.
An n-GaAs layer 3 is formed on a semi-insulating substrate 1 made of aAs.
, p-GaAs layer 4 and n Alo, 25Gao,
75A8 layers 5 are sequentially formed by the MBE method.

Next, as shown in FIG. 4(b), a predetermined pattern of Au
Emitter electrode 9 made of GeNi and Si○ on it
2 films 12, and then use this as a mask to form n-Al
The p-GaAs layer 4 is exposed by etching and removing the o, 2s Gao, and 7s AS layers 5, and at the same time, an emitter layer is formed. Next, using the 5102 film 12 as a mask, p-G
An AuZnNi layer 18 is formed on the aAs layer 4 in a self-aligned manner.

Next, as shown in FIG. 4(C), a photoresist film 17 with a predetermined pattern is formed, and using this as a mask, AuZ
After etching the nNi layer 18 to form a base electrode, the p-GaAs layer 4 and the n-GaAs are etched.
The surface of the s-layer 3 is removed, and an ohmic metal AuGeNi layer 11 is deposited from above on the surface of the n-GaAs layer 3 using the photoresist film 17 as a mask.

Next, the photoresist film 17 is dissolved in an organic solvent and lift-off is performed to form an emitter electrode, thereby producing a bipolar transistor having the structure shown in FIG.

(Problem to be Solved by the Invention) The cutoff frequency of a bipolar transistor can be expressed as follows. In equation (1), τ8 is the emitter time constant, and 7B is the base travel time, τ. is the collector travel time, τ. . is the collector time constant, and in equation (2), r is the base resistance,
CBo is the base-collector capacitance.

From equations (1) and (2), it can be seen that reducing τ8 is effective in increasing τ, and reducing r is effective in increasing f, but as for the base layer thickness, The two demands of tobacco are contradictory. In other words, if we reduce τ8 by making the base layer thinner, then r increases and fmax deteriorates significantly. It was very difficult to reduce the thickness below.

In addition, in the conventional example described above, n Alo, 25G
ao 75A8 layer 5 is etched to form p-GaAs layer 4
The step of forming an emitter layer by exposing the base (base surface exposing step) is one of the very important steps. That is, if the p-GaAs layer 4 is not sufficiently exposed, the contact resistance between the base layer and the base electrode is high, resulting in a high base resistance.

On the other hand, if the p-GaAs layer 4 is over-etched, the base layer becomes thinner, which also causes an increase in base resistance. Therefore, the quality of this process greatly influences the high speed and high frequency characteristics of the final transistor. Furthermore, the base layer is 70-1100
Since the wafer is as thin as n, variations in the amount of etching within the wafer are one of the causes of significantly reducing the uniformity of device characteristics. Conventionally, it has been difficult to perform this process over the entire wafer with sufficient controllability. The base layer is ~7
Needless to say, when the thickness is less than 0 nm, the base surface leveling process itself becomes even more difficult. Moreover, if the base layer becomes very thin, a problem arises in that the base electrode metal 18 diffuses and reaches the collector layer.

The purpose of the present invention is to solve these problems, to significantly reduce the heat generation, to make it possible to reduce the base layer thickness to ~70 nm or less, and to improve the device characteristics caused by the base surface leveling process. An object of the present invention is to provide a bipolar transistor with no variations and a method for manufacturing the same.

(Means for Solving the Problems) The present invention provides a bipolar transistor in which a collector layer, a base layer, and an emitter layer (or an emitter layer, a base layer, and a collector layer) are sequentially formed on a semi-insulating substrate. The layer contains Ga, AI as group III elements.
, At least one type of In, As as a group ■ element,
an intrinsic base layer made of a III+V group compound semiconductor containing at least one of P; and an external base layer made of C-doped GaAs having a hole concentration equal to or greater than that of the intrinsic base layer; The intrinsic base layer and the extrinsic base layer are bonded in a direction transverse to the stacking direction of the emitter layer, the base layer, and the collector layer.

Further, the method for manufacturing a bipolar transistor of the present invention includes:
a step of sequentially stacking a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer, and a first conductivity type third semiconductor layer on a semi-insulating substrate; and the third semiconductor layer. forming a mask with a predetermined pattern made of a first insulator on the layer; and removing the third semiconductor layer to a predetermined thickness by etching using the mask; a step of forming a side wall made of a solid material, and using the first and second insulators as masks, a portion of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer,
Alternatively, after removing the third semiconductor layer and the second semiconductor layer by etching, etching is performed on the first semiconductor layer by a molecular beam epitaxy method containing an organic group III element raw material as at least one of the raw material gases. the fourth of the second conductivity type
The method is characterized in that it includes a step of selectively forming a semiconductor layer.

(Function) The base resistance r of a bipolar transistor can generally be expressed as (3). In equation (3), R is the sheet resistance of the base layer, W
E is the emitter width, L is the emitter length, LBB is the distance between the emitter mesa and the base electrode, PC is the contact resistivity to the base electrode, LB is the base electrode width, L: (Pc/R,)
It is. Therefore, in order to reduce r, etc., it is necessary to reduce R8 and P, but in actual devices, the third term on the right side of equation (3) accounts for a very large proportion, and the PC is a particularly important issue.

1. One way to reduce this is to increase the p-type impurity concentration in the base layer. Since the MBE method has excellent controllability and uniformity of the grown film thickness and impurity concentration, it is particularly effective for crystal growth of compound semiconductor bipolar transistors. Be used as type impurity is ~5
When the concentration exceeds X10 am, there is a problem that diffusion into the emitter-side grown crystal increases (Y.C. Pao et al. (Y, C.).

Pao et al.), Journal of Applied Physics
d Physics), Vol. 60, 1986, p. 201).

ρ while solving the above problem. In order to reduce
It is effective to form an external base layer whose p-type impurity concentration and composition are set independently of the intrinsic base layer. Molecular beam epitaxy method (hereinafter referred to as
For example, T. Yamada et al. (T., Ya.
Mada et al.), Journal of Crystal Growth
1 Growth), Vol. 95, 1989, p. 145, and since selective growth is possible, it is considered to be very suitable for forming this external base layer.

The table below lists GaAs layers with different p-type impurity concentrations for ohmic metals (Ti/Pt/Au and Au).
The results of measuring the contact resistivity for Mn/Au) are shown.

In the above table, the Be-doped GaAs layer was formed by the MBE method, and the C-doped GaAs layer was formed by the MOMBE method. All contact resistivities are results for non-alloy. It can be seen that by forming a p-type GaAs layer with a high C concentration using the MOMBE method, a very low contact resistivity can be obtained even though no alloying is performed.

When the structure of the base layer is such that the intrinsic base layer and the selectively grown external base layer are in contact with each other from the lateral direction, as in the present invention, a particular problem is the contact resistance at the bonding interface between the two. . Figure 5 shows the contact resistance Rci and contact resistivity/'ci' at the bonding interface with the 4X10 cm +7) Be-doped layer (corresponding to the external base layer) formed by the MBE method, and the thickness W of the Be-doped GaAs layer.
(However, pci ” R, W).Here, B is set so that the bonding interface is almost perpendicular to each layer.
After removing a part of the e-doped GaAs layer by etching, a 200 nm C-doped GaAs layer was selectively grown using the MOMBE method to form a sample, and the TLM method (for example, C.K. Reeves et al. e
t al, ), IEE, Electron Device Letters (IEEE Electron
Device Letters), EDL-3 volume,
1982, p. 111).

From FIG. 5, the Be-doped GaAs layer and the C-doped GaAs layer
The contact resistivity at the bonding interface of the layers is 7 × 1000 cm
It is found that the increase in base resistance caused by contact resistance at the bonding interface between the intrinsic base layer and the external base layer can be sufficiently suppressed.

As explained above, in the bipolar transistor of the present invention, it can be expected that the base resistance will be significantly reduced. FIG. 6 shows the relationship between the base layer thickness WB and the base resistance r, and compares the bipolar transistor of the present invention with that of a conventional bipolar transistor. Emitter size is 1. gmX10μ
m, the base electrode width was 1.5 μm, the distance between the emitter mesa and the base electrode was 0.2.4 zm, and the base electrode metal was TiPtAu. The base impurity concentration of the conventional example is 4X10 cm
In addition, for the present invention, the impurity concentration of the intrinsic base layer and the external base layer (thickness 300 nm) is set to 4×10
cm and 4×10 am, and the bonding interface between them was assumed to be perpendicular to the emitter-base bonding surface. From FIG. 6, it can be seen that the base resistance is significantly reduced in the present invention.

FIG. 7 compares the relationship between the base electrode width LB and the base resistance r between the present invention and the conventional bipolar transistor when the base layer thickness WB is 40 nm and 80 nm. As shown in Figure 7, the effect of reducing base resistance becomes more important as the width of the base electrode becomes smaller, that is, as the device becomes finer, and this is important in improving the characteristics of bipolar transistors. It's very convenient.

Furthermore, in the present invention, there is no need to perform a base surface exposing process when forming the base electrode, and the external base region can be removed by etching up to the collector layer. Therefore, the intrinsic base layer can be easily made thinner in terms of device manufacturing. Furthermore, if the thickness of the regrown extrinsic base is increased to a certain extent, the variation in base resistance between elements caused by non-uniform film thickness in the extrinsic base region can be significantly reduced compared to the case of the conventional structure. At the same time, it is possible to prevent the base electrode metal from diffusing and reaching the collector layer.

At the same time, it is also possible to flatten the emitter and base to reduce disconnections in the wiring.

Note that although the above description has focused on the case where the bonding interface between the intrinsic base layer and the external base layer is perpendicular to the emitter-base bonding surface, the present invention is not limited to this, and the bonding interface in other states may be used. It goes without saying that the same effect can be obtained even if the two sides are formed (excluding the case where they are parallel).

(Example) Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining a bipolar transistor which is an embodiment of the present invention.

This semiconductor chip consists of a semi-insulating substrate 1 made of GaAs.
and a collector contact layer (3) made of n-GaAs.
X10 am , 400 nm)2 and n-GaAs
This is the true base layer consisting of (3-cut Ocm, 40n
m) 4 and an emitter layer (3 Ocm, 200 nm) consisting of n-Alo, 25Gao, 75A8, and n
- A grade consisting of AlxGa1-xA5 (x: 0.25→0).

layer (3×10 am, 50 nm) 6 and n-G
The external base layer (4X
10 am, 300 nm) 8, an emitter electrode 9 made of AuGeNi, a base electrode 10 made of TiPtAu, and a collector electrode 11 made of AuGeNi.
It is composed of a SiO2 film 12, an upper film 23, and an insulating region 14.

Next, a method for manufacturing this bipolar transistor will be explained.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the manufacturing method.

First, as shown in FIG. 2(a), n-GaAs layers 2 and 3, p-
GaAs layer 4, n-AI. , 25Ga, 7. As layer 5
, n-AlxGa1-xAs graded layer (x: 0.
25-+0)6, n After sequentially forming the GaAs layer 7 at a growth temperature of 600° C. by the MBE method, H is implanted into the portion other than the portion where the bipolar transistor is to be formed to form the insulating region 14.

Next, as shown in FIG. 2(b), the n-GaAs layer 7
An ohmic metal AuGeNi layer 9 is deposited on top of the layer 51.
02 film 12 and a photoresist film 1 having a predetermined pattern
After sequentially forming layers 5 and 5, using this photoresist film 15 as a mask, the SiO□ film 12 is etched with a dodecyl ion beam, and the AuGeNi layer 9 is sequentially etched by ion milling.
Remove.

Next, as shown in FIG. 2(c), after cleaning with an organic solvent to remove the photoresist film 15, using the 5102 film 12 as a mask, the n-GaAs layer 7, the n-AlxG
a,-.

The As layer 6 is removed by reactive ion beam etching using C12 as an etching gas, and n-Al is removed in the same manner until a predetermined thickness is achieved. , 25Gao, 75As
Etch layer 5. Subsequently, 8102 film 13 is applied to the entire surface.
After forming, this is removed by reactive ion beam etching using CF4 as an etching gas.
81 on the sides of the n-GaAs layer 7, the n-AlxGa1-xAs layer 6, and the n-Alo, 25Gao, 75AS layer 5.
02 film 13 is formed. In this case, SiO
2 films 13 films bottom 3 thin n-Al. , 2. Gao, 7. As
It is desirable that the layer 5 be completely depleted, and if the thickness is set to about several tens of nanometers, it will function as a protective layer. The effect is reported, for example, in Hayama et al., Institute of Electronics, Information and Communication Engineers Technical Report, Vol. ED89-147, 1989, p.67. Also, this thin n Alo, 25Ga
o, 7s A8 layer 5 has a base layer sheet resistance of 8102
It also functions to prevent local growth in the lower part of the membrane 13.

Next, as shown in FIG. 2(d), n Alo, 2. Gao, 7. AS layer 5
, p-GaA 44, and part of the n-GaAs layer 3 are sequentially etched and removed, and then trimethyl gallium (G
M using a(CHs)3) and solid As as growth raw materials
By the OMBE method, the p-GaAs layer 8 is selectively formed on the n-GaAs layer 3 at a growth temperature of 450 DEG C. using the SiO2 film 12 top 213 as a mask. Next, a photoresist film with a predetermined pattern is formed to cover the active region of the bipolar transistor, and using this as a mask, the insulating region 1 is formed.
After etching and removing the p-GaAs layer 8 on the p-GaAs layer 4, a photoresist film 16 is formed, and a Ti
A PtAu layer 10 is deposited.

Next, as shown in FIG. 2(e), after removing the photoresist film 16 by cleaning with an organic solvent, a photoresist film 17 with a predetermined pattern is formed so that the width of the base electrode becomes a predetermined value. Make it. Next, photoresist film 1
TiPtAu by ion milling using No. 7 as a mask.
Layer 10 is etched away, and p-GaAs layer 8 and n-
GaAs layer 3 is removed by etching to form n-GaA
The surface of the s-layer 2 is exposed. Subsequently, using the photoresist film 17 as a mask, an AuGeNi layer 11, which is an ohmic metal of the n-GaAs layer 2, is deposited from above.

Finally, the photoresist film 17 is dissolved in an organic solvent and lift-off is performed to obtain a bipolar transistor having the structure shown in FIG.

In addition, in the above-mentioned embodiment, the intrinsic base layer is p −
Although the invention has been described with respect to a layer made of GaAs, the present invention is not limited thereto. For example, it may be made of a graded base structure by gradually changing the A1 composition of an intrinsic base layer made of p-AlGaAs, an AlInAs/InGaAs system, or an InP layer. /InGaAs type heterojunction bipolar transistor, the intrinsic base layer is p-InGaAs.
or p -AlInGaAs or p
The present invention can be similarly applied to materials made of -InGaAsP, etc., and the effects are the same.

Further, in the above embodiments, an emitter-up type was described, but the present invention is not limited thereto, and can be similarly applied to a collector-up type.

(Effects of the Invention) As explained above, according to the present invention, the base resistance can be significantly reduced as shown in FIGS. 6 and 7, and the base layer can be made thinner. , the maximum oscillation frequency and cutoff frequency can be increased. In addition, since the base surface leveling process is not necessary, it is possible to prevent the increase in base resistance caused by it.
It is possible to suppress variations in base resistance over the entire wafer. As a result, a compound semiconductor bipolar transistor with excellent high-speed and high-frequency characteristics can be realized, and the uniformity of device characteristics within the wafer can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining the structure of an embodiment of a bipolar transistor according to the present invention, and FIGS. 2(a) to (e) illustrate a method of manufacturing the bipolar transistor of FIG. 1. FIG. 3 is a cross-sectional view of a semiconductor chip shown in the order of steps for the process, and FIG. 4 is a cross-sectional view of a semiconductor chip for explaining the structure of a conventional bipolar transistor.
a) to (C) are cross-sectional views of a semiconductor chip shown in the order of steps to explain the manufacturing method of the bipolar transistor of FIG. 3, and FIG. FIG. 6 is a diagram showing the dependence of the contact resistance and contact resistivity on the intrinsic base layer thickness at the junction interface. FIG. FIG. 7 is a diagram showing the relationship between base resistance and base electrode width in the present invention and conventional bipolar transistors. In each figure, 1... semi-insulating substrate (GaAs), 2
...n-GaAs collector contact layer, 3...n
-GaAs collector layer, 4-p-GaAs intrinsic base layer, 5-n-Alo, 2sGao, 7sAS engineered layer, 6-n-AlxGax-1As graded layer (x:
0.25-+0), 7-n-GaAs emitter contact layer, 8-p-Gahj part! Base layer, 9・AuGe
Ni emitter electrode, 10... TiPtAu base electrode, 1l-AuGeNi collector electrode, 12, 13...
SiO2 film, 14...insulating region, 15.16.17.
, , photoresist film, 18-AuZnNi layer.

Claims (2)

[Claims] (1) In a bipolar transistor in which a collector layer, a base layer, and an emitter layer (or an emitter layer, a base layer, and a collector layer) are sequentially formed on a semi-insulating substrate,
The p-type base layer is an intrinsic base layer made of a III-V compound semiconductor having at least one of Ga, Al, and In as a group III element and at least one of As and P as a group V element; An external base layer made of C-doped GaAs has a hole concentration equal to or greater than the intrinsic base layer, and the intrinsic base layer and the external base layer form an emitter layer, a base layer, and a collector layer. A bipolar transistor characterized by being bonded in a direction transverse to the stacking direction. (2) a first semiconductor layer of a first conductivity type on a semi-insulating substrate;
A step of sequentially stacking a second semiconductor layer of a second conductivity type and a third semiconductor layer of a first conductivity type, and forming a mask with a predetermined pattern made of a first insulator on the third semiconductor layer. and removing the third semiconductor layer to a predetermined thickness by etching using the mask,
forming a side wall made of a second insulator;
and a part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer, or the third semiconductor layer and the second semiconductor layer, using the second insulator as a mask. , after removal by etching, a fourth semiconductor layer of the second conductivity type is selectively formed on the first semiconductor layer by a molecular beam epitaxy method containing an organic group III element raw material in at least one of the raw material gases. A method for manufacturing a bipolar transistor, comprising the steps of: