JPH0483442A - Data transmitter/receiver - Google Patents

Abstract

PURPOSE:To allow this data transmitter/receiver to correspond to a terminal having a rapid processing speed with a sufficiently long interval by providing a delay means for delaying ON of an output signal from a counting means by a prescribed time when a transmission request signal has been already applied to a delay part at the time of turning on a power supply. CONSTITUTION:When a transmission request signal has been already applied to a delay part 31 at the time of turning on a power supply, ON of an output signal from a counting means 6 is delayed by a prescribed time through a delay means 7. Since a three-input OR gate 8 applies OR operation among the outputs Q6, Q7 of the counter 6 and the output, the inverse of Q, of a flip flop 7 obtained by delaying the signal Q6, Q7 by a prescribed time to a data transmission part as a transmission request signal IRS, a data transmission part 32 is prevented from sending data and generating a data error before the data transmitter/receiver starts normal operation at the time of turning on the power supply. Thereby, even when a terminal having a high processing speed is connected, the data transmitter/receiver can correspond to the terminal with a sufficiently long interval.

Description

[Detailed description of the invention] [Industrial application field] INDUSTRIAL APPLICATION This invention is utilized for the data transmission/reception apparatus of data communication.

〔overview〕

The present invention provides a data transmitting/receiving device in which, when the power is turned on and a transmission request signal has already been given from the own terminal, the processing speed is increased by delaying the turning on of the transmission request signal by a predetermined time and giving it to the data transmitting section. Even when a high-speed terminal is connected, a sufficient interval can be taken to cope with the connection.

[Conventional technology]

FIG. 4 is a block diagram of a delay section of a conventional data transmitting/receiving device. FIG. 5 is a timing chart of each signal waveform of a delay section of a conventional data transmitting/receiving device.

Conventionally, data transmitting/receiving devices sometimes receive surplus data on the opposite side immediately after turning off the transmission signal, so the terminal side sends information to the other side to prevent this surplus data from being recognized as data. ``Off'' of the request to send signal
After detecting this, the transmission request signal is delayed for a predetermined period of time and then sent to the data transmitting section with the "off" transmission request signal, and a predetermined pattern is sent to the delayed opening side, and the other side detects this predetermined pattern. If it does, it has a circuit that prevents it from being treated as data. Therefore, a circuit was required to delay the transmission request.

In this circuit, as shown in FIG. 4, the counter 6 inputs the transmission request signal RTS from the terminal side and outputs two types of outputs Q
6, the output signal of Q7 was output to the data transmitter as a transmission request signal. Further, the OR gate 11 inputs the transmission request signal RTS from the terminal side and the transmission enable signal IC3 inputted from the data transmitter, and outputs the transmission enable signal to the terminal side.

[Problem to be solved by the invention]

However, in such a conventional data transmitting/receiving device, when the data transmitting/receiving device is started with the transmission request signal RTS on the terminal side in the "on" state, the counter 6 is reset by the initialization signal CLR when the power is turned on, and no transmission is performed. Request signal IR3
is in the "on" state, so there is a drawback that the data transmitter may send out data and cause data errors before the data transmitting/receiving device starts operating normally.

Also, when connected to a terminal device with a fast processing speed, the fourth
The transmission request signal RTS from the terminal side shown in the figure has a fast interval, and the time from when the transmission request signal RTS turns "off" until it turns "on" is short, as shown in the partial element shown in FIG. For this reason, in the case of a data transmitting/receiving device that uses a circuit that delays the transmission request signal, the transmission request signal RTS on the terminal side is used to output the transmittable signal from the data transmitter as an "off J signal" in order to hold it for a certain period of time. As shown in part g of the transmittable signal OC8 shown in FIG. 5, the transmittable signal OC8 transmitted to the terminal side is momentarily "on" and data is sent, resulting in a data error.

The present invention solves the above-mentioned drawbacks. Even when a terminal with a high processing speed is connected, it can be handled with sufficient intervals, and even if a transmission request signal has already been given when the power is turned on, the data cannot be transmitted. It is an object of the present invention to provide a data transmitting/receiving device in which a data transmitting section does not transmit data before the transmitting/receiving device starts operating normally, thereby preventing data errors.

[Means to solve the problem]

The present invention includes a delay unit that is initialized when the power is turned on and includes a counting unit that outputs the “off” state of a transmission request signal input from its own terminal after a predetermined time delay, and an output signal of the counting unit that is input and transmitted. and a data transmitting unit that outputs a transmission enable signal, and the delay unit includes sending means for supplying the output transmission enable signal to the own terminal based on the transmission request signal, wherein the delay unit is configured to output a transmission enable signal when the power is turned on. The apparatus is characterized in that it includes a delay means for delaying turning on of the output signal of the counting means for a predetermined period of time when the transmission request signal has already been given.

Further, in the present invention, the sending means may include means for turning off the output transmission enable signal near the rising edge of the transmission request signal.

Further, in the present invention, the counting means includes a first flip-flop which inputs the transmission request signal to the input C, inputs the power supply voltage to the input terminal, and inputs the AND of the initialization signal and the power supply voltage to the input S. a first OR gate to which the transmission request signal and the signal of the output Q of the first flip-flop are input; a NAND gate to which the output of the first OR gate and the initialization signal are input; and a transmission clock signal. is input into one input, the output of this NAND gate is inputted to the clock signal input, the output of the NAND gate is inputted to the reset input, and one output signal is applied to the other input of the NOR gate. a counter that supplies an inverted signal to the input R of the first flip-flop; the delay means inputs the power supply voltage and the input S, inputs the initialization signal to the input R, and outputs the other output of the counter; A second flip-flop inputs a signal to input C, and inputs the two output signals of the counter and the signal of the output Q of the second flip-flop, and outputs the logical sum thereof as an output signal of the counting means. and a three-input OR gate, and the sending means may include means for inputting the signal of the output Q of the first flip-flop and the output enable signal and providing the logical sum thereof to the own terminal.

[Effect]

The delay means turns on the output signal of the counting means if the transmission request signal RTS has already been given when the power is turned on.
is delayed for a predetermined time.

As a result, even when a terminal with a high processing speed is connected, a sufficient interval can be provided.

In addition, when the generation means generates the "off" of the transmission enable signal IC3 near the rising edge of the transmission request signal, even if the transmission request signal is already given when the power is turned on, the data transmitting/receiving device may not start operating normally. This eliminates the possibility that the data transmitter sends out data and causes data errors.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a data transmitting/receiving device according to an embodiment of the present invention. FIG. 2 is a block diagram of the delay section of the data transmitting/receiving apparatus according to the present invention. In Figures 1 and 2,
The data transmitting/receiving device includes a delay unit 31 that is initialized when the power is turned on and includes a counting device that outputs the “off” transmission request signal RTS input from the own terminal device 20 after a predetermined time delay, and an output of the counting device. The delay unit 31 includes a data transmitter 32 that inputs a signal and outputs a transmittable signal IC3, and a transmitter that provides a transmitter request signal C8 to its own terminal device 20 based on the transmitter request signal RTS.

Here, the feature of the present invention is that the delay section 31 includes a delay means for delaying "on" of the output signal of the counting means for a predetermined period of time when the transmission request signal RTS has already been given when the power is turned on. It is in.

Further, in the present invention, the sending means includes means for generating the "off" state of the transmission enable signal IC3 from near the rising edge of the transmission request signals RT and S.

Further, in the present invention, the counting means includes an AND gate 1 which inputs the power supply voltage and the initialization signal CLR, and an output of the AND gate 1 which inputs the transmission request signal RTS to the input C and inputs the power supply voltage to the input terminal. A flip-flop 2 is used as a first flip-flop that inputs a signal to input S, an OR gate 3 is used as a first OR gate that inputs a transmission request signal RTS and a signal of the output Q of the flip-flop 2, and an output of the OR gate 3 and an initial a NAND gate 4 that inputs the conversion signal CLR, a NOR gate 5 that inputs the transmission clock signal ST to one input, and a NAND gate 5 that inputs the output of the NOR gate 5 to the clock signal input and resets the output of the NAND gate 4 to the input R.
The signal of the output Q7 is input to the other input of the NOR gate 5, and the inverted signal of the signal of the output Q7 is applied to the flip-flop 20.
a counter 6 applied to the input R, and the delay means includes:
Input the power supply voltage to input and input S, and input the initialization signal C.
A flip-flop 7 inputs LR to the input R and inputs the signal of the other output Q6 of the counter 6 to the input C, and the signals of the two outputs Q6 and Q7 of the counter 6 and the flip-flop 7
and the signal of output Q of
The sending means includes means for inputting the signal of the output Q of the flip-flop 2 and the transmittable signal C8, and providing the logical sum thereof to the own terminal device 20.

The operation of the data transmitting/receiving device having such a configuration will be explained. FIG. 3 is a timing chart of each signal waveform of the delay section of the data transmitting/receiving device of the present invention. In FIGS. 2 and 3, the transmission clock signal ST is input to the clock signal input C of the counter 6 via the NOR gate 5. In FIG. The signal of the output Q of the flip-flop 7, which inputs the signal of the output Q6 of the counter 6 to the clock signal input C, and the signals of the outputs Q6 and Q7 of the counter 6 are input to the 3-input OR gate 8.
Enter. The counter 6 is initialized by inputting the transmission clock signal ST through the NOR gate 5. The flip-flop 2 inputs the power supply voltage to its input terminal, and inputs the AND of the initialization signal CLR and the power supply voltage to its input S for initialization. The free-knob flop 7 inputs an initialization signal CLR to an input R, and inputs it to an input S for initialization. The NAND gate 4 inputs the transmission request signal RTS from the terminal via the OR gate 3 and the initialization signal CLR, and applies the NAND thereof to the input R of the count 6 to reset it. The NAND gate 4 inputs the signal of the output Q7 of the count 6 and the transmission clock signal ST from the terminal, and supplies the NOR thereof to the input C of the count 6 as a clock signal. Flip-flop 2 inputs the inverted signal of the signal of Q7 of count 6, and provides the signal of output Q to input R of counter 6 via OR gate 3 and NAND gate 4. The flip-flop 7 receives a transmission request signal R when the power is turned on.
When TS has already been given, the signal from the output Q6 of the counter 6 is input to the input C when the power is turned on, and the signal from the output Q is applied to the three-input OR gate 8 via the signal line S1. 3
The input OR gate 8 connects the signals of the outputs Q6 and Q7 of the counter 6 and the flip-flop 7 delayed by a predetermined time from this signal.
In order to provide the logical sum of the outputs of the data transmission unit 32 to the data transmission unit as the transmission request signal IR3, the data transmission unit 32 transmits data before the data transmission/reception device starts operating normally when the power is turned on, causing a data error. There is no.

Further, the OR gate 9 takes the logical sum of the transmittable signal IC3 from the data transmitter 32 and the signal of the output Q of the flip-flop 2, and changes the "off" state of the transmittable signal IC8 until the "off" state of the transmission request signal RTS. Advanced transmittable signal OC8
In order to provide the terminal device 20 with the following information, it is possible to sufficiently cope with the case where a terminal with a high processing speed is connected.

〔Effect of the invention〕

As described above, the present invention has the excellent effect of being able to respond with sufficient intervals even when a terminal with a high processing speed is connected.

Furthermore, even if a transmission request signal is already applied when the power is turned on, there is an advantage that the data transmitter does not transmit data and cause data errors before the data transmitter/receiver starts operating normally.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transmitting/receiving device according to an embodiment of the present invention. FIG. 2 is a block diagram of the delay section of the data transmitting/receiving device of the present invention. FIG. 3 is a timing chart of signal waveforms of each part of the delay section of the data transmitting/receiving device of the present invention. FIG. 4 is a schematic diagram of the main part of a conventional data transmitter/receiver. Figure () is a timing chart of the signal type of each part of the delay section of the conventional data transmitting/receiving device. 1... Ant game-1-12, 7... Flip-flop, 3.9.11.12... Or game-1, 4...
・Nando game, 5..., /Age 1, 6...
Counter, 8... 3-input OR gate, 20... Terminal bag, 30... Data transmitting/receiving device, 31... Delay section, 32... Data transmitting section, 33... Data reception part, CL, R...Initialization signal, IC3, OC3...Transmittable signal, IR3, RT S...Transmission request signal, S
l, S2...signal line, ST...transmission clock signal,
.

Claims (1)

[Scope of Claims] 1. A delay unit that is initialized when the power is turned on and includes a counting means that delays the "off" state of the transmission request signal input from the own terminal by a predetermined time and outputs the output signal, and an output signal of the counting means. and a data transmitting section that inputs a signal and outputs a transmittable signal, and the delay section supplies the output transmittable signal to the own terminal based on the transmission request signal. A data transmitting/receiving device characterized in that the section includes a delay means for delaying turning on of the output signal of the counting means for a predetermined period if the transmission request signal has already been applied when the power is turned on. 2. The data transmitting/receiving apparatus according to claim 1, wherein said sending means includes means for generating an "off" state of said output enable signal from near the rising edge of said transmission request signal. 3. The counting means includes a first flip-flop which inputs the transmission request signal to input C, inputs the power supply voltage to input D, and inputs the AND of the initialization signal and the power supply voltage to input S; A first OR gate receives the request signal and the signal of the output Q of the first flip-flop, a NAND gate receives the output of the first OR gate and the initialization signal, and one input receives the transmission clock signal. The output of this NAND gate is input to the clock signal input, the output of the NAND gate is input to the reset input, one output signal is applied to the other input of the NAND gate, and the inverted signal of this one output signal is input to the above. a counter applied to the input R of the first flip-flop, the delay means inputs the power supply voltage to the input D and the input S, inputs the initialization signal to the input R, and applies the other output signal of the counter to the input C. and a three-input OR gate that inputs the two output signals of the counter and the signal of the output Q of the second flip-flop and outputs the logical sum thereof as the output signal of the counting means. and the sending means outputs the output Q of the first flip-flop.
3. The data transmitting/receiving device according to claim 1, further comprising means for inputting the signal and the output transmittable signal and providing the logical sum thereof to the own terminal.