JPH0484439A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remarkably reduce a junction capacity between a semiconductor substrate and source.drain diffused layer by opening a contact hole to be opened for source.drain to a titanium silicide layer drawn on a filed oxide film from the source.drain. CONSTITUTION:Reverse conductivity type impurity to that of a semiconductor substrate is ion implanted in a titanium silicide layer and the substrate in a self-alignment manner with a gate electrode 4 and the second oxide film 7 of a sidewall as masks, and heat treated to form a high concentration diffused layer 12. In this case, since the impurity implanted in the titanium silicide is diffused in the silicide layer at a very fast speed during heat treating, a high concentration diffused layer 12 is formed in the substrate. After an interlayer film 13 is formed, a contact hole is opened on the layer 11. Then, after tungsten or tungsten silicide 14 is buried, metal wirings 15 are formed thereon, and the layer 11 is electrically connected to the wiring 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a source/drain diffusion layer of an MO8 type semiconductor device and its comparison wiring.

[Conventional technology]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of connecting source/drain diffusion layers of a conventional MO8 type semiconductor device and an upper metal wiring will be described with reference to the drawings.

FIG. 5 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in order of steps. FIG. 6 is a plan view of a semiconductor device manufactured by the manufacturing method shown in FIG.

A sectional view taken along line DD' in FIG. 6 is shown in FIG. 5e).

The steps will be explained below in order.

As shown in FIG. 5a), a field oxide film 2. After forming the gate oxide film 3, a polycrystalline silicon 4 with a thickness of about 200 OA is grown, then a first oxide film 5 with a thickness of about 1000 OA is grown, and the polycrystalline silicon is grown in a predetermined pattern. and the first oxide film 5 are simultaneously patterned to form the gate electrode 4. Next, using the gate electrode as a mask, a first impurity (P) having a conductivity type opposite to that of the semiconductor substrate is added.
In the case of a type substrate, for example, ion implantation of phosphorus) is performed, and 101
A low concentration diffusion layer 6 of about 8 to 10 "an"-" is formed.

As shown in FIG. 5b), a second oxide film 7 of 2,000 to 3,000 layers is grown on the semiconductor substrate by the CVD method.

As shown in FIG. 5C, the second oxide film 7 is etched back by anisotropic etching to expose the semiconductor substrate surface and leave the second oxide film 7 only on the side walls of the gate electrode. . Next, using the gate electrode 4 and the second oxide film 7 as a mask, a second impurity (P) having a conductivity type opposite to that of the semiconductor substrate is added.
In the case of a type substrate, for example, arsenic) is ion-implanted, and 10
A high concentration diffusion layer 12 of approximately 10 to 10 cm is formed.

Next, a titanium layer 10 of about 1000 layers is formed on the surface of the semiconductor substrate.

In FIG. 5d), a titanium silicide layer 11 is formed on the exposed surface of the semiconductor substrate by heat treatment.

Unreacted titanium is removed by etching with hydrogen peroxide solution.

After forming an interlayer insulating film 13 as shown in FIG. 5e), a contact hole is formed on the titanium silicide 11.

Next, after embedding tungsten or tungsten silicide 14, metal wiring 15 is formed on top of it, and the titanium silicide layer and metal wiring 15 are electrically connected.

FIG. 5e) is a sectional view of the final process when manufactured by a conventional manufacturing method.

[Problem to be solved by the invention]

In this conventional manufacturing method, unless the contact hole is always opened on the titanium silicide layer formed on the high concentration diffusion layer, the diffusion layer may leak at the contact hole portion. Therefore, the area of the diffusion layer is determined by the size of the contact hole and
The size includes the alignment margin between the end of the contact hole, the end of the gate electrode, and the end of the field (end of the diffusion layer).

Therefore, there is a problem that the junction capacitance between the semiconductor substrate and the diffusion layer increases. This junction capacitance increases when the impurity concentration of the semiconductor substrate is increased to prevent bunch-through between the source and drain when shortening the gate length of the transistor in order to improve the current driving ability of the transistor. Therefore, even if the gate length of the MOS transistor is reduced, the junction capacitance increases, resulting in a problem that an integrated circuit device that operates at high speed cannot be manufactured. moreover,
Since the contact hole is formed on the titanium silicide on the high concentration diffusion layer, the above-mentioned area is required, and there is a problem that a high density MOS transistor cannot be arranged.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a field region and an active region on a semiconductor substrate having a -conductivity type, forming a gate oxide film on the active region, and forming a predetermined pattern on the gate oxide film. forming a gate electrode and a first oxide film having the same pattern as the gate electrode; ion-implanting a first impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate in a self-aligned manner using the gate electrode as a mask; A step of forming a low concentration impurity diffusion layer, a second oxide film is grown on the semiconductor substrate and anisotropic etching is performed to leave the second oxide film only on the side walls of the gate electrode, and at the same time, the second oxide film is left only on the side walls of the gate electrode. A process of exposing the surface of the semiconductor substrate other than the area, a process of growing a polycrystalline silicon layer and then patterning the polycrystalline silicon layer into a predetermined shape, and a process of forming a titanium film on the entire surface, followed by heat treatment. , forming a titanium silicide layer on the top of the polycrystalline silicon and the exposed surface of the semiconductor substrate, removing the unreacted titanium layer, and adding a second impurity having a conductivity type opposite to that of the semiconductor substrate to the electrode and sidewalls; A step of implanting ions into the titanium silicide layer and the semiconductor substrate in a self-aligned manner using the second oxide film of the part as a mask, and a step of performing heat treatment to form a highly concentrated source/drain diffusion layer in the semiconductor substrate. and a step of growing an interlayer insulating film, forming a contact hole in the interlayer insulating film on the titanium silicide layer, and making an electrical connection to the upper metal wiring.

[Actual travel example]

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention in order of steps.

FIG. 2 shows the result of manufacturing by the manufacturing method shown in FIG. 1.
FIG. 2 is a plan view of a semiconductor device.

A sectional view taken along line AA' in FIG. 2 is shown in FIG. 2 f).

The steps will be explained below in order.

As shown in FIG. 1a), a field oxide film 2. After forming the gate oxide film 3, polycrystalline silicon 4 is grown to a thickness of approximately 2,000 wafers, and then a first oxide film 5 to a thickness of approximately 1,000 wafers is simultaneously patterned to form a gate electrode. Next, a first impurity of a conductivity type opposite to that of the semiconductor substrate (for example, phosphorus in the case of a P-type substrate) is ion-implanted in a self-aligned manner using the gate Tl pole as a mask.
A low concentration diffusion layer 6 of about 0 "an-" is formed.

As shown in FIG. 1C), 2,000 to 3,000 layers of second oxide 1!7 are grown on the semiconductor substrate by the CVD method.

As shown in FIG. 1C, the second oxide film 7 is etched back by anisotropic etching to expose the surface of the semiconductor substrate, and at the same time, the second oxide film 7 is formed only on the side walls of the gate electrode. leave. At this time, since the first oxide film 5 exists on the gate electrode 4, the surface of the gate electrode 4 is not exposed.

Next, polycrystalline silicon 8 is grown to a thickness of about 100 OA, and photoresist 9 is anisotropically etched with a mask into a predetermined shape. At this time, since the polycrystalline silicon layer 8 is thin,
The amount of overetching during etching can be kept small, and the diffusion layer is not etched to a large extent in areas where there is no photoresist 9.

The polycrystalline silicon layer 8 can be patterned arbitrarily on the field and on the gate electrode.

As shown in Fig. 1 d), a titanium layer of about 1000 layers is formed on the semiconductor substrate. As shown in Fig. 1 e), heat treatment is performed to form titanium silicide on the exposed semiconductor substrate surface and the upper part of the polycrystalline silicon 8. Form layer 11. Unreacted titanium is removed by etching.

At this time, the thickness of the titanium silicide layer can be controlled by the thickness of titanium and heat treatment, and is made to have a thickness of about 800 to 1000.

Next, an impurity having a conductivity type opposite to that of the semiconductor substrate (for example, As in the case of a P-type substrate) is added to the titanium silicide layer and the semiconductor substrate in a self-aligned manner using the gate electrode 4 and the second oxide film 7 on the side wall as a mask. Ion implantation inside and heat treatment 1
A high concentration diffusion layer 12 of about 0.020 to 10"cm is formed. At this time, the impurity injected into the titanium silicide diffuses very quickly in the silicide layer during heat treatment.
A highly concentrated diffusion layer 12 is formed in the semiconductor substrate.

As shown in FIG. 1f), after forming the interlayer gap 13, a contact hole is formed on the titanium silicide layer ll.

Next, after tungsten or tungsten silicide 14 is buried, a metal wiring 15 is formed on top of the tungsten or tungsten silicide 14, and electrical connection is made between the titanium silicide layer 11 and the metal wiring 15.

FIG. 1f) is a sectional view of the final process when manufactured by the manufacturing method of the present invention.

Examples of utilization of the manufacturing method of the present invention will be described below with reference to the drawings.

3a), b) and FIG. 4 a), b) show a plan view and a sectional view of a semiconductor device manufactured by the manufacturing method of the present invention.

In Figure 3 a) and b), two MOS transistors are arranged close to each other, the drain and source of each transistor are close to each other, and contact holes are opened for each source and drain. The case is shown below.

According to the manufacturing method of the present invention, a polycrystalline silicon layer 8 is patterned to cover a part of the gate electrode, a titanium silicide layer 11 is grown on top of the polycrystalline silicon layer 8, and a contact hole is formed in the titanium silicide layer 11. , to obtain electrical connection with the upper metal wiring. In this case, the contact hole is opened through the first oxide film 5 to the titanium silicide layer 11 existing above the gate electrode.

FIGS. 4a) and 4b) show a case where two MOS transistors are arranged at a certain distance from each other and the diffusion layers arranged facing each other are both sources.

According to the manufacturing method of the present invention, the polycrystalline silicon layer 8 is patterned so as to connect the sources of two opposing MOS transistors, and a titanium silicide layer 11 is formed on top of the polycrystalline silicon layer 8. A contact hole is opened to obtain electrical connection with the upper metal wiring 15. In this case, the source contact hole is opened to the titanium silicide layer 11 on the field oxide film.

Also, Tr, 2 in Fig. 3, Tr, 1°Tr, 2 in Fig. 4
Most of the area of the contact hole connected to the drain of
This is a region of the titanium silicide layer 11 drawn out onto the field, and the area of the drain diffusion layer is kept small.

〔Effect of the invention〕

As explained above, in the manufacturing method of the present invention, the contact holes opened to the source and drain of the MoS transistor are opened to the titanium silicide layer drawn out from the source and drain onto the field oxide film. The area of the source/drain diffusion layer can be minimized.

Therefore, the junction capacitance between the semiconductor substrate and the source/drain diffusion layer can be significantly reduced, making it possible to operate the integrated circuit device at high speed.

In addition, the titanium silicide layer drawn from the source/drain can be formed to the top of the gate electrode via the oxide film.
Since two contact holes can be formed on the titanium silicide layer in that region, there is no need to provide the area necessary for forming the contact holes on the diffusion layer, and the area of the transistor can be reduced.

Therefore, there is an effect that the degree of integration of the integrated circuit device can be improved.

Furthermore, since the polycrystalline silicon can be patterned arbitrarily, separate diffusion layers can be connected with a two-layer wiring structure of polycrystalline silicon and titanium silicide layers, allowing higher-density device arrangement.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the process order for explaining the present invention in detail. FIG. 2 is a plan view for explaining the present invention in detail. Figure 3 2 Figure 4 shows the arrangement of MoS transistors utilizing the present invention! ! FIG. 2 is a plan view and a cross-sectional view for explaining. FIG. 5 is a cross-sectional view showing a conventional manufacturing method in order of steps. FIG. 6 is a plan view for explaining the conventional manufacturing method. ■...Semiconductor substrate, 2...Field oxide film, 3...Gate oxide film, 4...Gate electrode, 5...First Oxide film, 6...
Low concentration impurity diffusion layer, 7... second oxide film, 8.
...Polycrystalline silicon layer, 9...Photoresist, 10...Titanium layer, 11...
Titanium silicide layer, 12... High concentration impurity diffusion layer, 13... Interlayer insulating film, 14...
Tungsten or tungsten silicide, 15... mark, metal wiring. Agent: Susumu Uchihara, patent attorney! Figure 1. Figure 1. Figure 3. Figure 1.

Claims (1)

[Claims] A step of forming a field region and an active region on a semiconductor substrate having one conductivity type, forming a gate oxide film on the active region, and forming a gate electrode in a predetermined pattern on the gate oxide film and a gate electrode in the same pattern as the gate electrode. a step of forming a first oxide film, and a step of ion-implanting a first impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate in a self-aligned manner using the gate electrode as a mask to form a low concentration impurity diffusion layer. and a step of growing a second oxide film on the semiconductor substrate and leaving the second oxide film only on the side walls of the gate electrode by anisotropic etching, and at the same time exposing the surface of the semiconductor substrate other than the gate electrode and field area. After growing the polycrystalline silicon layer, a process of patterning the polycrystalline silicon layer into a predetermined shape, and after forming a titanium film on the entire surface, heat treatment is performed to remove the upper part of the polycrystalline silicon and the exposed semiconductor. A step of forming a titanium silicide layer on the surface of the substrate, removing the unreacted titanium layer, and adding a second impurity having a conductivity type opposite to that of the semiconductor substrate using the electrode electrode and the second oxide film on the side wall as a mask. A step of implanting ions into the titanium silicide layer and the semiconductor substrate in a consistent manner, a step of performing heat treatment to form a highly concentrated source/drain diffusion layer in the semiconductor substrate, and a step of growing an interlayer insulating film to remove the titanium silicide layer. 1. A method for manufacturing a semiconductor device, comprising the step of forming a contact hole in an interlayer insulating film on a layer and electrically connecting it to an upper metal wiring.